From 25474167e5b247d1b91fbf802c5b396a63ae705e Mon Sep 17 00:00:00 2001 From: Giacomo Gabrielli Date: Tue, 16 Oct 2018 16:04:08 +0100 Subject: arch,cpu: Add vector predicate registers Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector Extension (SVE), introduce the notion of a predicate register file. This changeset adds this feature across architectures and CPU models. Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946 Signed-off-by: Giacomo Gabrielli Reviewed-on: https://gem5-review.googlesource.com/c/13715 Maintainer: Andreas Sandberg Reviewed-by: Jason Lowe-Power --- src/arch/SConscript | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src/arch/SConscript') diff --git a/src/arch/SConscript b/src/arch/SConscript index 5ea7a6a75..ed583aa5a 100644 --- a/src/arch/SConscript +++ b/src/arch/SConscript @@ -1,6 +1,6 @@ # -*- mode:python -*- -# Copyright (c) 2016 ARM Limited +# Copyright (c) 2016-2017 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -226,6 +226,8 @@ Export('ISADesc') DebugFlag('IntRegs') DebugFlag('FloatRegs') DebugFlag('VecRegs') +DebugFlag('VecPredRegs') DebugFlag('CCRegs') DebugFlag('MiscRegs') -CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'CCRegs', 'MiscRegs' ]) +CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'VecRegs', 'VecPredRegs', + 'CCRegs', 'MiscRegs' ]) -- cgit v1.2.3