From 7d0344704a9ecc566d82ad43ec44b4becbaf4d77 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 24 Jan 2014 15:29:30 -0600 Subject: arch, cpu: Add support for flattening misc register indexes. With ARMv8 support the same misc register id results in accessing different registers depending on the current mode of the processor. This patch adds the same orthogonality to the misc register file as the others (int, float, cc). For all the othre ISAs this is currently a null-implementation. Additionally, a system variable is added to all the ISA objects. --- src/arch/alpha/AlphaISA.py | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/arch/alpha/AlphaISA.py') diff --git a/src/arch/alpha/AlphaISA.py b/src/arch/alpha/AlphaISA.py index 64c9e4733..d85354704 100644 --- a/src/arch/alpha/AlphaISA.py +++ b/src/arch/alpha/AlphaISA.py @@ -35,9 +35,13 @@ # # Authors: Andreas Sandberg +from m5.params import * +from m5.proxy import * from m5.SimObject import SimObject class AlphaISA(SimObject): type = 'AlphaISA' cxx_class = 'AlphaISA::ISA' cxx_header = "arch/alpha/isa.hh" + + system = Param.System(Parent.any, "System this ISA object belongs to") -- cgit v1.2.3