From f6742ea26e1a1cac21b486c7c5adad6fb6304e92 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Sun, 25 Jan 2015 07:22:26 -0500 Subject: cpu: Remove all notion that we know when the cpu is misspeculating. We have no way of knowing if a CPU model is on the wrong path with our execute-in-execute CPU models. Don't pretend that we do. --- src/arch/alpha/faults.cc | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) (limited to 'src/arch/alpha/faults.cc') diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc index 6375b0bfb..2928f8d65 100644 --- a/src/arch/alpha/faults.cc +++ b/src/arch/alpha/faults.cc @@ -147,8 +147,7 @@ DtbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) // on VPTE loads (instead of locking the registers until IPR_VA is // read, like the EV5). The EV6 approach is cleaner and seems to // work with EV5 PAL code, but not the other way around. - if (!tc->misspeculating() && - reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) { + if (reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) { // set VA register with faulting address tc->setMiscRegNoEffect(IPR_VA, vaddr); @@ -172,11 +171,9 @@ void ItbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) { if (FullSystem) { - if (!tc->misspeculating()) { - tc->setMiscRegNoEffect(IPR_ITB_TAG, pc); - tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM, - tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3)); - } + tc->setMiscRegNoEffect(IPR_ITB_TAG, pc); + tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM, + tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3)); } AlphaFault::invoke(tc); -- cgit v1.2.3