From 689cab36c90b56b3c8a7cda16d758acdd89f9de1 Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Wed, 7 Mar 2007 15:04:31 -0500
Subject: *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg

--HG--
extra : convert_revision : f799b65f1b2a6bf43605e6870b0f39b473dc492b
---
 src/arch/alpha/interrupts.hh | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

(limited to 'src/arch/alpha/interrupts.hh')

diff --git a/src/arch/alpha/interrupts.hh b/src/arch/alpha/interrupts.hh
index 0500714ad..6453edf97 100644
--- a/src/arch/alpha/interrupts.hh
+++ b/src/arch/alpha/interrupts.hh
@@ -112,13 +112,13 @@ namespace AlphaISA
             int ipl = 0;
             int summary = 0;
 
-            if (tc->readMiscReg(IPR_ASTRR))
+            if (tc->readMiscRegNoEffect(IPR_ASTRR))
                 panic("asynchronous traps not implemented\n");
 
-            if (tc->readMiscReg(IPR_SIRR)) {
+            if (tc->readMiscRegNoEffect(IPR_SIRR)) {
                 for (int i = INTLEVEL_SOFTWARE_MIN;
                      i < INTLEVEL_SOFTWARE_MAX; i++) {
-                    if (tc->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
+                    if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
                         // See table 4-19 of 21164 hardware reference
                         ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
                         summary |= (ULL(1) << i);
@@ -138,12 +138,12 @@ namespace AlphaISA
                 }
             }
 
-            if (ipl && ipl > tc->readMiscReg(IPR_IPLR)) {
+            if (ipl && ipl > tc->readMiscRegNoEffect(IPR_IPLR)) {
                 newIpl = ipl;
                 newSummary = summary;
                 newInfoSet = true;
                 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
-                        tc->readMiscReg(IPR_IPLR), ipl, summary);
+                        tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
 
                 return new InterruptFault;
             } else {
@@ -154,8 +154,8 @@ namespace AlphaISA
         void updateIntrInfo(ThreadContext *tc)
         {
             assert(newInfoSet);
-            tc->setMiscReg(IPR_ISR, newSummary);
-            tc->setMiscReg(IPR_INTID, newIpl);
+            tc->setMiscRegNoEffect(IPR_ISR, newSummary);
+            tc->setMiscRegNoEffect(IPR_INTID, newIpl);
             newInfoSet = false;
         }
 
-- 
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