From 5e8287d2e2eaf058495442ea9e32fafc343a0b53 Mon Sep 17 00:00:00 2001 From: Nathanael Premillieu Date: Wed, 5 Apr 2017 12:46:06 -0500 Subject: arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/2700 --- src/arch/alpha/isa/branch.isa | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch/alpha/isa/branch.isa') diff --git a/src/arch/alpha/isa/branch.isa b/src/arch/alpha/isa/branch.isa index b60cb6d1e..d4b6db043 100644 --- a/src/arch/alpha/isa/branch.isa +++ b/src/arch/alpha/isa/branch.isa @@ -130,7 +130,7 @@ output decoder {{ Jump::branchTarget(ThreadContext *tc) const { PCState pc = tc->pcState(); - uint64_t Rb = tc->readIntReg(_srcRegIdx[0]); + uint64_t Rb = tc->readIntReg(_srcRegIdx[0].regIdx); pc.set((Rb & ~3) | (pc.pc() & 1)); return pc; } -- cgit v1.2.3