From 689cab36c90b56b3c8a7cda16d758acdd89f9de1 Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Wed, 7 Mar 2007 15:04:31 -0500
Subject: *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg

--HG--
extra : convert_revision : f799b65f1b2a6bf43605e6870b0f39b473dc492b
---
 src/arch/alpha/isa/fp.isa | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/arch/alpha/isa/fp.isa')

diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index c845ea442..a350aa05f 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -46,7 +46,7 @@ output exec {{
     inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
     {
         Fault fault = NoFault;	// dummy... this ipr access should not fault
-        if (!EV5::ICSR_FPE(xc->readMiscRegWithEffect(AlphaISA::IPR_ICSR))) {
+        if (!EV5::ICSR_FPE(xc->readMiscReg(AlphaISA::IPR_ICSR))) {
             fault = new FloatEnableFault;
         }
         return fault;
@@ -229,7 +229,7 @@ def template FloatingPointExecute {{
             %(code)s;
         } else {
             fesetround(getC99RoundingMode(
-                           xc->readMiscReg(AlphaISA::MISCREG_FPCR)));
+                           xc->readMiscRegNoEffect(AlphaISA::MISCREG_FPCR)));
             %(code)s;
             fesetround(FE_TONEAREST);
         }
-- 
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