From 672d6a4b98165952e0afa0057f851f150bc657ec Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 20 Dec 2010 16:24:40 -0500 Subject: Style: Replace some tabs with spaces. --- src/arch/alpha/isa/decoder.isa | 10 +++++----- src/arch/alpha/isa/fp.isa | 30 +++++++++++++++--------------- src/arch/alpha/isa/main.isa | 28 ++++++++++++++-------------- src/arch/alpha/isa/pal.isa | 8 ++++---- 4 files changed, 38 insertions(+), 38 deletions(-) (limited to 'src/arch/alpha/isa') diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index 36458a047..d829ad744 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -100,7 +100,7 @@ decode OPCODE default Unknown::unknown() { format IntegerOperate { - 0x10: decode INTFUNC { // integer arithmetic operations + 0x10: decode INTFUNC { // integer arithmetic operations 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }}); 0x40: addlv({{ @@ -173,7 +173,7 @@ decode OPCODE default Unknown::unknown() { }}); } - 0x11: decode INTFUNC { // integer logical operations + 0x11: decode INTFUNC { // integer logical operations 0x00: and({{ Rc = Ra & Rb_or_imm; }}); 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }}); @@ -291,7 +291,7 @@ decode OPCODE default Unknown::unknown() { }}); } - 0x13: decode INTFUNC { // integer multiplies + 0x13: decode INTFUNC { // integer multiplies 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp); 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp); 0x30: umulh({{ @@ -301,7 +301,7 @@ decode OPCODE default Unknown::unknown() { }}, IntMultOp); 0x40: mullv({{ // 32-bit multiply with trap on overflow - int64_t Rax = Ra.sl; // sign extended version of Ra.sl + int64_t Rax = Ra.sl; // sign extended version of Ra.sl int64_t Rbx = Rb_or_imm.sl; int64_t tmp = Rax * Rbx; // To avoid overflow, all the upper 32 bits must match @@ -587,7 +587,7 @@ decode OPCODE default Unknown::unknown() { format BasicOperateWithNopCheck { 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp); 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp); - 0x014: FailUnimpl::itoff(); // VAX-format conversion + 0x014: FailUnimpl::itoff(); // VAX-format conversion } } } diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa index f9abd9b68..b1d01724d 100644 --- a/src/arch/alpha/isa/fp.isa +++ b/src/arch/alpha/isa/fp.isa @@ -32,9 +32,9 @@ // // Floating-point instructions // -// Note that many FP-type instructions which do not support all the -// various rounding & trapping modes use the simpler format -// BasicOperateWithNopCheck. +// Note that many FP-type instructions which do not support all the +// various rounding & trapping modes use the simpler format +// BasicOperateWithNopCheck. // output exec {{ @@ -45,7 +45,7 @@ output exec {{ #if FULL_SYSTEM inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) { - Fault fault = NoFault; // dummy... this ipr access should not fault + Fault fault = NoFault; // dummy... this ipr access should not fault if (!ICSR_FPE(xc->readMiscReg(IPR_ICSR))) { fault = new FloatEnableFault; } @@ -71,11 +71,11 @@ output header {{ public: /// Alpha FP rounding modes. enum RoundingMode { - Chopped = 0, ///< round toward zero + Chopped = 0, ///< round toward zero Minus_Infinity = 1, ///< round toward minus infinity - Normal = 2, ///< round to nearest (default) - Dynamic = 3, ///< use FPCR setting (in instruction) - Plus_Infinity = 3 ///< round to plus inifinity (in FPCR) + Normal = 2, ///< round to nearest (default) + Dynamic = 3, ///< use FPCR setting (in instruction) + Plus_Infinity = 3 ///< round to plus inifinity (in FPCR) }; /// Alpha FP trapping modes. @@ -84,10 +84,10 @@ output header {{ /// the assembly modifier is V rather than U. enum TrappingMode { /// default: nothing enabled - Imprecise = 0, ///< no modifier + Imprecise = 0, ///< no modifier /// underflow/overflow traps enabled, inexact disabled - Underflow_Imprecise = 1, ///< /U or /V - Underflow_Precise = 5, ///< /SU or /SV + Underflow_Imprecise = 1, ///< /U or /V + Underflow_Precise = 5, ///< /SU or /SV /// underflow/overflow and inexact traps enabled Underflow_Inexact_Precise = 7 ///< /SUI or /SVI }; @@ -192,10 +192,10 @@ output decoder {{ } const int AlphaFP::alphaToC99RoundingMode[] = { - M5_FE_TOWARDZERO, // Chopped - M5_FE_DOWNWARD, // Minus_Infinity - M5_FE_TONEAREST, // Normal - M5_FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR + M5_FE_TOWARDZERO, // Chopped + M5_FE_DOWNWARD, // Minus_Infinity + M5_FE_TONEAREST, // Normal + M5_FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR }; const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" }; diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa index fa0086fc7..077520139 100644 --- a/src/arch/alpha/isa/main.isa +++ b/src/arch/alpha/isa/main.isa @@ -102,30 +102,30 @@ namespace AlphaISA; // Universal (format-independent) fields def bitfield PALMODE <32:32>; -def bitfield OPCODE <31:26>; -def bitfield RA <25:21>; -def bitfield RB <20:16>; +def bitfield OPCODE <31:26>; +def bitfield RA <25:21>; +def bitfield RB <20:16>; // Memory format def signed bitfield MEMDISP <15: 0>; // displacement def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned) // Memory-format jumps -def bitfield JMPFUNC <15:14>; // function code (disp<15:14>) -def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>) +def bitfield JMPFUNC <15:14>; // function code (disp<15:14>) +def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>) // Branch format def signed bitfield BRDISP <20: 0>; // displacement // Integer operate format(s>; -def bitfield INTIMM <20:13>; // integer immediate (literal) -def bitfield IMM <12:12>; // immediate flag -def bitfield INTFUNC <11: 5>; // function code -def bitfield RC < 4: 0>; // dest reg +def bitfield INTIMM <20:13>; // integer immediate (literal) +def bitfield IMM <12:12>; // immediate flag +def bitfield INTFUNC <11: 5>; // function code +def bitfield RC < 4: 0>; // dest reg // Floating-point operate format -def bitfield FA <25:21>; -def bitfield FB <20:16>; +def bitfield FA <25:21>; +def bitfield FB <20:16>; def bitfield FP_FULLFUNC <15: 5>; // complete function code def bitfield FP_TRAPMODE <15:13>; // trapping mode def bitfield FP_ROUNDMODE <12:11>; // rounding mode @@ -133,10 +133,10 @@ def bitfield FP_FULLFUNC <15: 5>; // complete function code def bitfield FP_SRCTYPE <10: 9>; // source reg type def bitfield FP_SHORTFUNC < 8: 5>; // short function code def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code -def bitfield FC < 4: 0>; // dest reg +def bitfield FC < 4: 0>; // dest reg // PALcode format -def bitfield PALFUNC <25: 0>; // function code +def bitfield PALFUNC <25: 0>; // function code // EV5 PAL instructions: // HW_LD/HW_ST @@ -154,7 +154,7 @@ def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk def bitfield HW_REI_MBZ <13: 0>; // must be zero // HW_MTPR/MW_MFPR -def bitfield HW_IPR_IDX <15:0>; // IPR index +def bitfield HW_IPR_IDX <15:0>; // IPR index // M5 instructions def bitfield M5FUNC <7:0>; diff --git a/src/arch/alpha/isa/pal.isa b/src/arch/alpha/isa/pal.isa index c6c0fa95c..53e0d6193 100644 --- a/src/arch/alpha/isa/pal.isa +++ b/src/arch/alpha/isa/pal.isa @@ -84,10 +84,10 @@ output header {{ class CallPalBase : public AlphaStaticInst { protected: - int palFunc; ///< Function code part of instruction - int palOffset; ///< Target PC, offset from IPR_PAL_BASE - bool palValid; ///< is the function code valid? - bool palPriv; ///< is this call privileged? + int palFunc; ///< Function code part of instruction + int palOffset; ///< Target PC, offset from IPR_PAL_BASE + bool palValid; ///< is the function code valid? + bool palPriv; ///< is this call privileged? /// Constructor. CallPalBase(const char *mnem, ExtMachInst _machInst, -- cgit v1.2.3