From 719f9a6d4fba16af38dcfd62b25a4d708156699f Mon Sep 17 00:00:00 2001
From: Giacomo Gabrielli <Giacomo.Gabrielli@arm.com>
Date: Tue, 7 Dec 2010 16:19:57 -0800
Subject: O3: Make all instructions that write a misc. register not perform the
 write until commit.

ARM instructions updating cumulative flags (ARM FP exceptions and saturation
flags) are not serialized.

Added aliases for ARM FP exceptions and saturation flags in FPSCR.  Removed
write accesses to the FP condition codes for most ARM VFP instructions: only
VCMP and VCMPE instructions update the FP condition codes.  Removed a potential
cause of seg. faults in the O3 model for NEON memory macro-ops (ARM).
---
 src/arch/alpha/isa/fp.isa | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/arch/alpha/isa')

diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index ed04d2a50..f9abd9b68 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -229,7 +229,7 @@ def template FloatingPointExecute {{
             %(code)s;
         } else {
             m5_fesetround(getC99RoundingMode(
-                           xc->readMiscRegNoEffect(MISCREG_FPCR)));
+                           xc->readMiscReg(MISCREG_FPCR)));
             %(code)s;
             m5_fesetround(M5_FE_TONEAREST);
         }
-- 
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