From 82f5723c7a8b245e1f60190a78b7fe383c2caf9b Mon Sep 17 00:00:00 2001
From: Nathan Binkert <nate@binkert.org>
Date: Sat, 27 Sep 2008 21:03:47 -0700
Subject: alpha: Clean up namespace usage.

---
 src/arch/alpha/isa/decoder.isa | 8 ++++----
 src/arch/alpha/isa/fp.isa      | 4 ++--
 src/arch/alpha/isa/main.isa    | 6 +++---
 3 files changed, 9 insertions(+), 9 deletions(-)

(limited to 'src/arch/alpha/isa')

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index dc30039b2..270940df2 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -638,7 +638,7 @@ decode OPCODE default Unknown::unknown() {
         /* Rb is a fake dependency so here is a fun way to get
          * the parser to understand that.
          */
-                Ra = xc->readMiscReg(AlphaISA::IPR_CC) + (Rb & 0);
+                Ra = xc->readMiscReg(IPR_CC) + (Rb & 0);
 
 #else
                 Ra = curTick;
@@ -690,7 +690,7 @@ decode OPCODE default Unknown::unknown() {
     0x00: CallPal::call_pal({{
         if (!palValid ||
             (palPriv
-             && xc->readMiscReg(AlphaISA::IPR_ICM) != AlphaISA::mode_kernel)) {
+             && xc->readMiscReg(IPR_ICM) != mode_kernel)) {
             // invalid pal function code, or attempt to do privileged
             // PAL call in non-kernel mode
             fault = new UnimplementedOpcodeFault;
@@ -701,8 +701,8 @@ decode OPCODE default Unknown::unknown() {
             bool dopal = xc->simPalCheck(palFunc);
 
             if (dopal) {
-                xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, NPC);
-                NPC = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + palOffset;
+                xc->setMiscReg(IPR_EXC_ADDR, NPC);
+                NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset;
             }
         }
     }}, IsNonSpeculative);
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index 8b13f8dd7..ed04d2a50 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -46,7 +46,7 @@ output exec {{
     inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
     {
         Fault fault = NoFault;	// dummy... this ipr access should not fault
-        if (!AlphaISA::ICSR_FPE(xc->readMiscReg(AlphaISA::IPR_ICSR))) {
+        if (!ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
             fault = new FloatEnableFault;
         }
         return fault;
@@ -229,7 +229,7 @@ def template FloatingPointExecute {{
             %(code)s;
         } else {
             m5_fesetround(getC99RoundingMode(
-                           xc->readMiscRegNoEffect(AlphaISA::MISCREG_FPCR)));
+                           xc->readMiscRegNoEffect(MISCREG_FPCR)));
             %(code)s;
             m5_fesetround(M5_FE_TONEAREST);
         }
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index d72dfe34a..5231712c8 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -173,11 +173,11 @@ def operands {{
     # Int regs default to unsigned, but code should not count on this.
     # For clarity, descriptions that depend on unsigned behavior should
     # explicitly specify '.uq'.
-    'Ra': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RA] : RA',
+    'Ra': ('IntReg', 'uq', 'PALMODE ? reg_redir[RA] : RA',
            'IsInteger', 1),
-    'Rb': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RB] : RB',
+    'Rb': ('IntReg', 'uq', 'PALMODE ? reg_redir[RB] : RB',
            'IsInteger', 2),
-    'Rc': ('IntReg', 'uq', 'PALMODE ? AlphaISA::reg_redir[RC] : RC',
+    'Rc': ('IntReg', 'uq', 'PALMODE ? reg_redir[RC] : RC',
            'IsInteger', 3),
     'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
     'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
-- 
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