From a5c4eb3de9deb3a71a6a5230a25ff5962e584980 Mon Sep 17 00:00:00 2001
From: Mitch Hayenga <mitch.hayenga@arm.com>
Date: Wed, 30 Sep 2015 11:14:19 -0500
Subject: isa,cpu: Add support for FS SMT Interrupts

Adds per-thread interrupt controllers and thread/context logic
so that interrupts properly get routed in SMT systems.
---
 src/arch/alpha/isa/decoder.isa | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/arch/alpha/isa')

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index c77ca434f..e61bb43ff 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -943,7 +943,7 @@ decode OPCODE default Unknown::unknown() {
             0x01: quiesce({{
                 // Don't sleep if (unmasked) interrupts are pending
                 Interrupts* interrupts =
-                    xc->tcBase()->getCpuPtr()->getInterruptController();
+                    xc->tcBase()->getCpuPtr()->getInterruptController(0);
                 if (interrupts->checkInterrupts(xc->tcBase())) {
                     PseudoInst::quiesceSkip(xc->tcBase());
                 } else {
-- 
cgit v1.2.3