From 038217049a952a67f29b79c416a35d89fea31f70 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Tue, 31 Oct 2006 03:37:01 -0500
Subject: Move IntrFlag into the MiscRegFile and get rid of specialized
 accessor functions.

--HG--
extra : convert_revision : e0d12a150b01d05de9bc02bcbc7c22797975a5b9
---
 src/arch/alpha/isa/decoder.isa | 8 ++++----
 src/arch/alpha/isa/main.isa    | 5 +++--
 2 files changed, 7 insertions(+), 6 deletions(-)

(limited to 'src/arch/alpha/isa')

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 5bd19b677..93b941d72 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -661,12 +661,12 @@ decode OPCODE default Unknown::unknown() {
 #if FULL_SYSTEM
         format BasicOperate {
             0xe000: rc({{
-                Ra = xc->readIntrFlag();
-                xc->setIntrFlag(0);
+                Ra = IntrFlag;
+                IntrFlag = 0;
             }}, IsNonSpeculative, IsUnverifiable);
             0xf000: rs({{
-                Ra = xc->readIntrFlag();
-                xc->setIntrFlag(1);
+                Ra = IntrFlag;
+                IntrFlag = 1;
             }}, IsNonSpeculative, IsUnverifiable);
         }
 #else
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 2024b1117..1df6ac603 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -183,8 +183,9 @@ def operands {{
     'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
     'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
     'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
-    'Runiq': ('ControlReg', 'uq', 'TheISA::Uniq_DepTag', None, 1),
-    'FPCR':  (' ControlReg', 'uq', 'TheISA::Fpcr_DepTag', None, 1),
+    'Runiq': ('ControlReg', 'uq', 'AlphaISA::Uniq_DepTag', None, 1),
+    'FPCR':  ('ControlReg', 'uq', 'AlphaISA::Fpcr_DepTag', None, 1),
+    'IntrFlag': ('ControlReg', 'uq', 'AlphaISA::Intr_Flag_DepTag', None, 1),
     # The next two are hacks for non-full-system call-pal emulation
     'R0':  ('IntReg', 'uq', '0', None, 1),
     'R16': ('IntReg', 'uq', '16', None, 1),
-- 
cgit v1.2.3


From ece796ab8af23705f3f4d7bd12ee623f3961c99e Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Tue, 31 Oct 2006 16:02:28 -0500
Subject: Make the IPRs use regular miscreg indexes, and make a table or two to
 find the miscreg index of a specific IPR.

--HG--
extra : convert_revision : dd235261e7086d6667b1b2bdc4a81b2573e21d53
---
 src/arch/alpha/isa/decoder.isa | 16 ++++++++++++++--
 src/arch/alpha/isa/main.isa    |  1 +
 2 files changed, 15 insertions(+), 2 deletions(-)

(limited to 'src/arch/alpha/isa')

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 93b941d72..852f483e0 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -745,7 +745,13 @@ decode OPCODE default Unknown::unknown() {
         0: OpcdecFault::hw_mfpr();
         format HwMoveIPR {
             1: hw_mfpr({{
-                Ra = xc->readMiscRegWithEffect(ipr_index, fault);
+                int miscRegIndex = IprToMiscRegIndex[ipr_index];
+                if(miscRegIndex < 0 ||
+                    (miscRegIndex >= MinWriteOnlyIpr &&
+                     miscRegIndex <= MaxWriteOnlyIpr))
+                        fault = new UnimplementedOpcodeFault;
+                else
+                    Ra = xc->readMiscRegWithEffect(ipr_index, fault);
             }}, IsIprAccess);
         }
     }
@@ -754,7 +760,13 @@ decode OPCODE default Unknown::unknown() {
         0: OpcdecFault::hw_mtpr();
         format HwMoveIPR {
             1: hw_mtpr({{
-                xc->setMiscRegWithEffect(ipr_index, Ra);
+                int miscRegIndex = IprToMiscRegIndex[ipr_index];
+                if(miscRegIndex < 0 ||
+                    (miscRegIndex >= MinReadOnlyIpr &&
+                     miscRegIndex <= MaxWriteOnlyIpr))
+                        fault = new UnimplementedOpcodeFault;
+                else
+                    xc->setMiscRegWithEffect(ipr_index, Ra);
                 if (traceData) { traceData->setData(Ra); }
             }}, IsIprAccess);
         }
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 1df6ac603..06d3e8243 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -71,6 +71,7 @@ output exec {{
 #if FULL_SYSTEM
 #include "sim/pseudo_inst.hh"
 #endif
+#include "arch/alpha/ipr.hh"
 #include "base/fenv.hh"
 #include "config/ss_compatible_fp.hh"
 #include "cpu/base.hh"
-- 
cgit v1.2.3


From 44f2c05118f46b996d13d7c3eac3227a8141e3fe Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Tue, 31 Oct 2006 16:18:54 -0500
Subject: Forgot to change the index.

--HG--
extra : convert_revision : 5a444e635d20bcca445a10e43592b6c10d25e879
---
 src/arch/alpha/isa/decoder.isa | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/arch/alpha/isa')

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 852f483e0..0cbe38ceb 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -751,7 +751,7 @@ decode OPCODE default Unknown::unknown() {
                      miscRegIndex <= MaxWriteOnlyIpr))
                         fault = new UnimplementedOpcodeFault;
                 else
-                    Ra = xc->readMiscRegWithEffect(ipr_index, fault);
+                    Ra = xc->readMiscRegWithEffect(miscRegIndex, fault);
             }}, IsIprAccess);
         }
     }
@@ -766,7 +766,7 @@ decode OPCODE default Unknown::unknown() {
                      miscRegIndex <= MaxWriteOnlyIpr))
                         fault = new UnimplementedOpcodeFault;
                 else
-                    xc->setMiscRegWithEffect(ipr_index, Ra);
+                    xc->setMiscRegWithEffect(miscRegIndex, Ra);
                 if (traceData) { traceData->setData(Ra); }
             }}, IsIprAccess);
         }
-- 
cgit v1.2.3


From fb5ba85abbf3791498faab3328a73b3725dfc839 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Tue, 31 Oct 2006 17:50:57 -0500
Subject: Make two simple utility functions to determine if a MiscReg index
 corresponding to an IPR is readable or writable.

--HG--
extra : convert_revision : 89eebba5eec01e629213997d24c734a6acad0ecb
---
 src/arch/alpha/isa/decoder.isa | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

(limited to 'src/arch/alpha/isa')

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 0cbe38ceb..550aa62a3 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -746,9 +746,7 @@ decode OPCODE default Unknown::unknown() {
         format HwMoveIPR {
             1: hw_mfpr({{
                 int miscRegIndex = IprToMiscRegIndex[ipr_index];
-                if(miscRegIndex < 0 ||
-                    (miscRegIndex >= MinWriteOnlyIpr &&
-                     miscRegIndex <= MaxWriteOnlyIpr))
+                if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex))
                         fault = new UnimplementedOpcodeFault;
                 else
                     Ra = xc->readMiscRegWithEffect(miscRegIndex, fault);
@@ -761,9 +759,7 @@ decode OPCODE default Unknown::unknown() {
         format HwMoveIPR {
             1: hw_mtpr({{
                 int miscRegIndex = IprToMiscRegIndex[ipr_index];
-                if(miscRegIndex < 0 ||
-                    (miscRegIndex >= MinReadOnlyIpr &&
-                     miscRegIndex <= MaxWriteOnlyIpr))
+                if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex))
                         fault = new UnimplementedOpcodeFault;
                 else
                     xc->setMiscRegWithEffect(miscRegIndex, Ra);
-- 
cgit v1.2.3


From 39de635fbfa281c2fa70b65833825e2559d029b9 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Tue, 31 Oct 2006 18:19:45 -0500
Subject: Check for out of range IPR values as well.

--HG--
extra : convert_revision : 9ca241bb71d8a1d022e54485383a88d2abece663
---
 src/arch/alpha/isa/decoder.isa | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

(limited to 'src/arch/alpha/isa')

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 550aa62a3..e4cf96767 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -745,8 +745,10 @@ decode OPCODE default Unknown::unknown() {
         0: OpcdecFault::hw_mfpr();
         format HwMoveIPR {
             1: hw_mfpr({{
-                int miscRegIndex = IprToMiscRegIndex[ipr_index];
-                if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex))
+                miscRegIndex >= NumInternalProcRegs)
+                int miscRegIndex = (ipr_index < NumInternalProcRegs) ?
+                        IprToMiscRegIndex[ipr_index] : -1;
+                if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) ||
                         fault = new UnimplementedOpcodeFault;
                 else
                     Ra = xc->readMiscRegWithEffect(miscRegIndex, fault);
@@ -758,7 +760,8 @@ decode OPCODE default Unknown::unknown() {
         0: OpcdecFault::hw_mtpr();
         format HwMoveIPR {
             1: hw_mtpr({{
-                int miscRegIndex = IprToMiscRegIndex[ipr_index];
+                int miscRegIndex = (ipr_index < NumInternalProcRegs) ?
+                        IprToMiscRegIndex[ipr_index] : -1;
                 if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex))
                         fault = new UnimplementedOpcodeFault;
                 else
-- 
cgit v1.2.3


From 1dd903e856e2e9995a85ac79e6519ff2d1f4d790 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Tue, 31 Oct 2006 18:39:17 -0500
Subject: Fix another typo

--HG--
extra : convert_revision : ad7058babf2a13bfe543e05f2662dc49a18a8b8b
---
 src/arch/alpha/isa/decoder.isa | 1 -
 1 file changed, 1 deletion(-)

(limited to 'src/arch/alpha/isa')

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index e4cf96767..c5f47aaa2 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -745,7 +745,6 @@ decode OPCODE default Unknown::unknown() {
         0: OpcdecFault::hw_mfpr();
         format HwMoveIPR {
             1: hw_mfpr({{
-                miscRegIndex >= NumInternalProcRegs)
                 int miscRegIndex = (ipr_index < NumInternalProcRegs) ?
                         IprToMiscRegIndex[ipr_index] : -1;
                 if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) ||
-- 
cgit v1.2.3


From 1543c3d0a11d77ac82658fdace755a0967d32cbb Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Tue, 31 Oct 2006 18:51:26 -0500
Subject: More typos! I need to get nfs to work.

--HG--
extra : convert_revision : f5693e96d376254f777fb0cce7b5be3d36efbea9
---
 src/arch/alpha/isa/decoder.isa | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'src/arch/alpha/isa')

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index c5f47aaa2..584d64a3d 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -748,6 +748,7 @@ decode OPCODE default Unknown::unknown() {
                 int miscRegIndex = (ipr_index < NumInternalProcRegs) ?
                         IprToMiscRegIndex[ipr_index] : -1;
                 if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) ||
+                    miscRegIndex >= NumInternalProcRegs)
                         fault = new UnimplementedOpcodeFault;
                 else
                     Ra = xc->readMiscRegWithEffect(miscRegIndex, fault);
@@ -761,7 +762,8 @@ decode OPCODE default Unknown::unknown() {
             1: hw_mtpr({{
                 int miscRegIndex = (ipr_index < NumInternalProcRegs) ?
                         IprToMiscRegIndex[ipr_index] : -1;
-                if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex))
+                if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex)
+                    miscRegIndex >= NumInternalProcRegs)
                         fault = new UnimplementedOpcodeFault;
                 else
                     xc->setMiscRegWithEffect(miscRegIndex, Ra);
-- 
cgit v1.2.3


From f3ba6d20f6070c30418866e627e2418f39b433dd Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Tue, 31 Oct 2006 18:59:50 -0500
Subject: Arg!

--HG--
extra : convert_revision : 8328d002780c0291e7eb264076a62084de88b7a5
---
 src/arch/alpha/isa/decoder.isa | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/arch/alpha/isa')

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 584d64a3d..f5483d9c0 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -762,7 +762,7 @@ decode OPCODE default Unknown::unknown() {
             1: hw_mtpr({{
                 int miscRegIndex = (ipr_index < NumInternalProcRegs) ?
                         IprToMiscRegIndex[ipr_index] : -1;
-                if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex)
+                if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) ||
                     miscRegIndex >= NumInternalProcRegs)
                         fault = new UnimplementedOpcodeFault;
                 else
-- 
cgit v1.2.3


From 2b11b4735761cdb5fcf32bbe0fb1cd96b7498db0 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 1 Nov 2006 16:44:45 -0500
Subject: Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing
 register file functions to not take faults

--HG--
extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
---
 src/arch/alpha/isa/decoder.isa | 8 ++++----
 src/arch/alpha/isa/fp.isa      | 2 +-
 2 files changed, 5 insertions(+), 5 deletions(-)

(limited to 'src/arch/alpha/isa')

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index f5483d9c0..fcf022ce1 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -629,7 +629,7 @@ decode OPCODE default Unknown::unknown() {
         /* Rb is a fake dependency so here is a fun way to get
          * the parser to understand that.
          */
-                Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC, fault) + (Rb & 0);
+                Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC) + (Rb & 0);
 
 #else
                 Ra = curTick;
@@ -681,7 +681,7 @@ decode OPCODE default Unknown::unknown() {
     0x00: CallPal::call_pal({{
         if (!palValid ||
             (palPriv
-             && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
+             && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM) != AlphaISA::mode_kernel)) {
             // invalid pal function code, or attempt to do privileged
             // PAL call in non-kernel mode
             fault = new UnimplementedOpcodeFault;
@@ -693,7 +693,7 @@ decode OPCODE default Unknown::unknown() {
 
             if (dopal) {
                 xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC);
-                NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
+                NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE) + palOffset;
             }
         }
     }}, IsNonSpeculative);
@@ -751,7 +751,7 @@ decode OPCODE default Unknown::unknown() {
                     miscRegIndex >= NumInternalProcRegs)
                         fault = new UnimplementedOpcodeFault;
                 else
-                    Ra = xc->readMiscRegWithEffect(miscRegIndex, fault);
+                    Ra = xc->readMiscRegWithEffect(miscRegIndex);
             }}, IsIprAccess);
         }
     }
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index b4339a1b7..103f85775 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -46,7 +46,7 @@ output exec {{
     inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
     {
         Fault fault = NoFault;	// dummy... this ipr access should not fault
-        if (!EV5::ICSR_FPE(xc->readMiscRegWithEffect(AlphaISA::IPR_ICSR, fault))) {
+        if (!EV5::ICSR_FPE(xc->readMiscRegWithEffect(AlphaISA::IPR_ICSR))) {
             fault = new FloatEnableFault;
         }
         return fault;
-- 
cgit v1.2.3


From 6f78d494101e0ebd542d8fe836df21d104374c33 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 1 Nov 2006 18:46:18 -0500
Subject: Fix a range check on the ipr_index.

--HG--
extra : convert_revision : 84e25abd4bb2de0c877c883804d39feb019c7030
---
 src/arch/alpha/isa/decoder.isa | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/arch/alpha/isa')

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index fcf022ce1..be6f574a9 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -745,7 +745,7 @@ decode OPCODE default Unknown::unknown() {
         0: OpcdecFault::hw_mfpr();
         format HwMoveIPR {
             1: hw_mfpr({{
-                int miscRegIndex = (ipr_index < NumInternalProcRegs) ?
+                int miscRegIndex = (ipr_index < MaxInternalProcRegs) ?
                         IprToMiscRegIndex[ipr_index] : -1;
                 if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) ||
                     miscRegIndex >= NumInternalProcRegs)
@@ -760,7 +760,7 @@ decode OPCODE default Unknown::unknown() {
         0: OpcdecFault::hw_mtpr();
         format HwMoveIPR {
             1: hw_mtpr({{
-                int miscRegIndex = (ipr_index < NumInternalProcRegs) ?
+                int miscRegIndex = (ipr_index < MaxInternalProcRegs) ?
                         IprToMiscRegIndex[ipr_index] : -1;
                 if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) ||
                     miscRegIndex >= NumInternalProcRegs)
-- 
cgit v1.2.3


From b04a2653f941fd8174760da156b601bf8a2de2ef Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Mon, 6 Nov 2006 19:09:23 -0500
Subject: Got rid of obsolete ivlb and ivle psuedo instructions.

--HG--
extra : convert_revision : c3c2dd5a6e7181ad94194146d7fa2b33b21074fb
---
 src/arch/alpha/isa/decoder.isa | 6 ------
 1 file changed, 6 deletions(-)

(limited to 'src/arch/alpha/isa')

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index be6f574a9..7014d4c22 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -795,12 +795,6 @@ decode OPCODE default Unknown::unknown() {
             0x04: quiesceTime({{
                 R0 = AlphaPseudo::quiesceTime(xc->tcBase());
             }}, IsNonSpeculative, IsUnverifiable);
-            0x10: ivlb({{
-                AlphaPseudo::ivlb(xc->tcBase());
-            }}, No_OpClass, IsNonSpeculative);
-            0x11: ivle({{
-                AlphaPseudo::ivle(xc->tcBase());
-            }}, No_OpClass, IsNonSpeculative);
             0x20: m5exit_old({{
                 AlphaPseudo::m5exit_old(xc->tcBase());
             }}, No_OpClass, IsNonSpeculative);
-- 
cgit v1.2.3


From 232c3f1b270aa04b924442bb6520c65c5a1414e1 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Thu, 9 Nov 2006 21:30:48 -0500
Subject: Moved the Alpha MiscRegFile into it's own file, and got rid of the
 Alpha specific DepTag constants.

--HG--
extra : convert_revision : e4af5e2fb2a6953f8837ad9bda309b7d6fa7abfb
---
 src/arch/alpha/isa/fp.isa   |  2 +-
 src/arch/alpha/isa/main.isa | 11 +++--------
 2 files changed, 4 insertions(+), 9 deletions(-)

(limited to 'src/arch/alpha/isa')

diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index 103f85775..3b5575f62 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -229,7 +229,7 @@ def template FloatingPointExecute {{
             %(code)s;
         } else {
             fesetround(getC99RoundingMode(
-                           xc->readMiscReg(AlphaISA::Fpcr_DepTag)));
+                           xc->readMiscReg(AlphaISA::MISCREG_FPCR)));
             %(code)s;
             fesetround(FE_TONEAREST);
         }
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 06d3e8243..6e65cf9d3 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -184,9 +184,9 @@ def operands {{
     'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
     'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
     'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
-    'Runiq': ('ControlReg', 'uq', 'AlphaISA::Uniq_DepTag', None, 1),
-    'FPCR':  ('ControlReg', 'uq', 'AlphaISA::Fpcr_DepTag', None, 1),
-    'IntrFlag': ('ControlReg', 'uq', 'AlphaISA::Intr_Flag_DepTag', None, 1),
+    'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
+    'FPCR':  ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
+    'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
     # The next two are hacks for non-full-system call-pal emulation
     'R0':  ('IntReg', 'uq', '0', None, 1),
     'R16': ('IntReg', 'uq', '16', None, 1),
@@ -216,11 +216,6 @@ output header {{
         /// live here and not in the AlphaISA namespace.
         enum DependenceTags {
             FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
-            Fpcr_DepTag = AlphaISA::Fpcr_DepTag,
-            Uniq_DepTag = AlphaISA::Uniq_DepTag,
-            Lock_Flag_DepTag = AlphaISA::Lock_Flag_DepTag,
-            Lock_Addr_DepTag = AlphaISA::Lock_Addr_DepTag,
-            IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag
         };
 
         /// Constructor.
-- 
cgit v1.2.3