From 719f9a6d4fba16af38dcfd62b25a4d708156699f Mon Sep 17 00:00:00 2001 From: Giacomo Gabrielli Date: Tue, 7 Dec 2010 16:19:57 -0800 Subject: O3: Make all instructions that write a misc. register not perform the write until commit. ARM instructions updating cumulative flags (ARM FP exceptions and saturation flags) are not serialized. Added aliases for ARM FP exceptions and saturation flags in FPSCR. Removed write accesses to the FP condition codes for most ARM VFP instructions: only VCMP and VCMPE instructions update the FP condition codes. Removed a potential cause of seg. faults in the O3 model for NEON memory macro-ops (ARM). --- src/arch/alpha/locked_mem.hh | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/arch/alpha/locked_mem.hh') diff --git a/src/arch/alpha/locked_mem.hh b/src/arch/alpha/locked_mem.hh index 86958e4c5..24d028b54 100644 --- a/src/arch/alpha/locked_mem.hh +++ b/src/arch/alpha/locked_mem.hh @@ -55,8 +55,8 @@ template inline void handleLockedRead(XC *xc, Request *req) { - xc->setMiscRegNoEffect(MISCREG_LOCKADDR, req->getPaddr() & ~0xf); - xc->setMiscRegNoEffect(MISCREG_LOCKFLAG, true); + xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf); + xc->setMiscReg(MISCREG_LOCKFLAG, true); } @@ -70,13 +70,13 @@ handleLockedWrite(XC *xc, Request *req) req->setExtraData(2); } else { // standard store conditional - bool lock_flag = xc->readMiscRegNoEffect(MISCREG_LOCKFLAG); - Addr lock_addr = xc->readMiscRegNoEffect(MISCREG_LOCKADDR); + bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG); + Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR); if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { // Lock flag not set or addr mismatch in CPU; // don't even bother sending to memory system req->setExtraData(0); - xc->setMiscRegNoEffect(MISCREG_LOCKFLAG, false); + xc->setMiscReg(MISCREG_LOCKFLAG, false); // the rest of this code is not architectural; // it's just a debugging aid to help detect // livelock by warning on long sequences of failed -- cgit v1.2.3