From 689cab36c90b56b3c8a7cda16d758acdd89f9de1 Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Wed, 7 Mar 2007 15:04:31 -0500
Subject: *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg

--HG--
extra : convert_revision : f799b65f1b2a6bf43605e6870b0f39b473dc492b
---
 src/arch/alpha/miscregfile.cc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'src/arch/alpha/miscregfile.cc')

diff --git a/src/arch/alpha/miscregfile.cc b/src/arch/alpha/miscregfile.cc
index 67f6c98e4..1af97adcf 100644
--- a/src/arch/alpha/miscregfile.cc
+++ b/src/arch/alpha/miscregfile.cc
@@ -61,7 +61,7 @@ namespace AlphaISA
     }
 
     MiscReg
-    MiscRegFile::readReg(int misc_reg)
+    MiscRegFile::readRegNoEffect(int misc_reg)
     {
         switch(misc_reg) {
           case MISCREG_FPCR:
@@ -87,7 +87,7 @@ namespace AlphaISA
     }
 
     MiscReg
-    MiscRegFile::readRegWithEffect(int misc_reg, ThreadContext *tc)
+    MiscRegFile::readReg(int misc_reg, ThreadContext *tc)
     {
         switch(misc_reg) {
           case MISCREG_FPCR:
@@ -112,7 +112,7 @@ namespace AlphaISA
     }
 
     void
-    MiscRegFile::setReg(int misc_reg, const MiscReg &val)
+    MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val)
     {
         switch(misc_reg) {
           case MISCREG_FPCR:
@@ -143,7 +143,7 @@ namespace AlphaISA
     }
 
     void
-    MiscRegFile::setRegWithEffect(int misc_reg, const MiscReg &val,
+    MiscRegFile::setReg(int misc_reg, const MiscReg &val,
             ThreadContext *tc)
     {
         switch(misc_reg) {
-- 
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