From b569f8f0ed8dcf32347f0d4f68d2d7572a5d1353 Mon Sep 17 00:00:00 2001 From: Korey Sewell Date: Tue, 12 May 2009 15:01:14 -0400 Subject: inorder-bpred: edits to handle non-delay-slot ISAs Changes so that InOrder can work for a non-delay-slot ISA like Alpha. Typically, changes have to do with handling misspeculated branches at different points in pipeline --- src/arch/alpha/process.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/arch/alpha/process.cc') diff --git a/src/arch/alpha/process.cc b/src/arch/alpha/process.cc index 093d83d8a..93df459ae 100644 --- a/src/arch/alpha/process.cc +++ b/src/arch/alpha/process.cc @@ -166,11 +166,11 @@ AlphaLiveProcess::argsInit(int intSize, int pageSize) tc->setPC(prog_entry); tc->setNextPC(prog_entry + sizeof(MachInst)); -#if THE_ISA != ALPHA_ISA //e.g. MIPS or Sparc + // MIPS/Sparc need NNPC for delay slot handling, while + // Alpha has no delay slots... However, CPU models + // cycle PCs by PC=NPC, NPC=NNPC, etc. so setting this + // here ensures CPU-Model Compatibility across board tc->setNextNPC(prog_entry + (2 * sizeof(MachInst))); -#endif - - } void -- cgit v1.2.3