From 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 Mon Sep 17 00:00:00 2001 From: Yasuko Eckert Date: Tue, 15 Oct 2013 14:22:44 -0400 Subject: cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. --- src/arch/alpha/registers.hh | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src/arch/alpha/registers.hh') diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh index 92ba22ee8..3fd774cf7 100644 --- a/src/arch/alpha/registers.hh +++ b/src/arch/alpha/registers.hh @@ -53,6 +53,9 @@ typedef uint64_t FloatRegBits; // control register file contents typedef uint64_t MiscReg; +// dummy typedef since we don't have CC regs +typedef uint8_t CCReg; + union AnyReg { IntReg intreg; @@ -91,6 +94,7 @@ const int NumFloatArchRegs = 32; const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; const int NumFloatRegs = NumFloatArchRegs; +const int NumCCRegs = 0; const int NumMiscRegs = NUM_MISCREGS; const int TotalNumRegs = @@ -101,7 +105,8 @@ enum DependenceTags { // 0..31 are the integer regs 0..31 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Reg_Base) FP_Reg_Base = NumIntRegs, - Misc_Reg_Base = FP_Reg_Base + NumFloatRegs, + CC_Reg_Base = FP_Reg_Base + NumFloatRegs, + Misc_Reg_Base = CC_Reg_Base + NumCCRegs, // NumCCRegs == 0 Max_Reg_Index = Misc_Reg_Base + NumMiscRegs + NumInternalProcRegs }; -- cgit v1.2.3