From 608641e23c7f2288810c3f23a1a63790b664f2ab Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Sun, 26 Jul 2015 10:21:20 -0500 Subject: cpu: implements vector registers This adds a vector register type. The type is defined as a std::array of a fixed number of uint64_ts. The isa_parser.py has been modified to parse vector register operands and generate the required code. Different cpus have vector register files now. --- src/arch/alpha/registers.hh | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'src/arch/alpha/registers.hh') diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh index 3fd774cf7..665ea30c7 100644 --- a/src/arch/alpha/registers.hh +++ b/src/arch/alpha/registers.hh @@ -56,6 +56,12 @@ typedef uint64_t MiscReg; // dummy typedef since we don't have CC regs typedef uint8_t CCReg; +// vector register file entry type +typedef uint64_t VectorRegElement; +const int NumVectorRegElements = 0; +const int VectorRegBytes = NumVectorRegElements * sizeof(VectorRegElement); +typedef std::array VectorReg; + union AnyReg { IntReg intreg; @@ -95,6 +101,7 @@ const int NumFloatArchRegs = 32; const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; const int NumFloatRegs = NumFloatArchRegs; const int NumCCRegs = 0; +const int NumVectorRegs = 0; const int NumMiscRegs = NUM_MISCREGS; const int TotalNumRegs = @@ -106,7 +113,8 @@ enum DependenceTags { // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Reg_Base) FP_Reg_Base = NumIntRegs, CC_Reg_Base = FP_Reg_Base + NumFloatRegs, - Misc_Reg_Base = CC_Reg_Base + NumCCRegs, // NumCCRegs == 0 + Vector_Reg_Base = CC_Reg_Base + NumCCRegs, // NumCCRegs == 0 + Misc_Reg_Base = Vector_Reg_Base + NumCCRegs, // NumVectorRegs == 0 Max_Reg_Index = Misc_Reg_Base + NumMiscRegs + NumInternalProcRegs }; -- cgit v1.2.3