From 1caed1465470269c36897904edddf8d4dc9765b1 Mon Sep 17 00:00:00 2001 From: Vincentius Robby Date: Wed, 8 Aug 2007 18:38:19 -0400 Subject: alpha: Quick fix for things related to TLB MRU cache. simple-timing test for ALPHA_FS breaks. --HG-- extra : convert_revision : 5a1b05cddd480849913da81a3b3931fec16485a8 --- src/arch/alpha/tlb.hh | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'src/arch/alpha/tlb.hh') diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh index 5be7eab59..a4255f3c5 100644 --- a/src/arch/alpha/tlb.hh +++ b/src/arch/alpha/tlb.hh @@ -61,7 +61,7 @@ namespace AlphaISA int nlu; // not last used entry (for replacement) void nextnlu() { if (++nlu >= size) nlu = 0; } - PTE *lookup(Addr vpn, uint8_t asn) const; + PTE *lookup(Addr vpn, uint8_t asn); public: TLB(const std::string &name, int size); @@ -92,6 +92,12 @@ namespace AlphaISA // Most recently used page table entries PTE *PTECache[3]; inline void flushCache() { memset(PTECache, 0, 3 * sizeof(PTE*)); } + inline PTE* updateCache(PTE *pte) { + PTECache[2] = PTECache[1]; + PTECache[1] = PTECache[0]; + PTECache[0] = pte; + return pte; + } }; class ITB : public TLB @@ -106,7 +112,7 @@ namespace AlphaISA ITB(const std::string &name, int size); virtual void regStats(); - Fault translate(RequestPtr &req, ThreadContext *tc) const; + Fault translate(RequestPtr &req, ThreadContext *tc); }; class DTB : public TLB @@ -129,7 +135,7 @@ namespace AlphaISA DTB(const std::string &name, int size); virtual void regStats(); - Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const; + Fault translate(RequestPtr &req, ThreadContext *tc, bool write); }; } -- cgit v1.2.3