From 608641e23c7f2288810c3f23a1a63790b664f2ab Mon Sep 17 00:00:00 2001
From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Sun, 26 Jul 2015 10:21:20 -0500
Subject: cpu: implements vector registers

This adds a vector register type.  The type is defined as a std::array of a
fixed number of uint64_ts.  The isa_parser.py has been modified to parse vector
register operands and generate the required code.  Different cpus have vector
register files now.
---
 src/arch/alpha/utility.cc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/arch/alpha/utility.cc')

diff --git a/src/arch/alpha/utility.cc b/src/arch/alpha/utility.cc
index 2dfe00f96..b0a503828 100644
--- a/src/arch/alpha/utility.cc
+++ b/src/arch/alpha/utility.cc
@@ -73,6 +73,7 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
 
     // Would need to add condition-code regs if implemented
     assert(NumCCRegs == 0);
+    assert(NumVectorRegs == 0);
 
     // Copy misc. registers
     copyMiscRegs(src, dest);
-- 
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