From 230b892fa3f484a46f4cd77f889f8793416b91e2 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 18 Oct 2018 17:34:08 -0700 Subject: arch: cpu: Stop passing around misc registers by reference. These values are all basic integers (specifically uint64_t now), and so passing them by const & is actually less efficient since there's a extra level of indirection and an extra value, and the same sized value (a 64 bit pointer vs. a 64 bit int) is being passed around. Change-Id: Ie9956b8dc4c225068ab1afaba233ec2b42b76da3 Reviewed-on: https://gem5-review.googlesource.com/c/13626 Maintainer: Gabe Black Reviewed-by: Jason Lowe-Power --- src/arch/alpha/isa.cc | 5 ++--- src/arch/alpha/isa.hh | 7 +++---- 2 files changed, 5 insertions(+), 7 deletions(-) (limited to 'src/arch/alpha') diff --git a/src/arch/alpha/isa.cc b/src/arch/alpha/isa.cc index 32d1aff65..685ddd479 100644 --- a/src/arch/alpha/isa.cc +++ b/src/arch/alpha/isa.cc @@ -114,7 +114,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid) } void -ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid) +ISA::setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid) { switch (misc_reg) { case MISCREG_FPCR: @@ -140,8 +140,7 @@ ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid) } void -ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc, - ThreadID tid) +ISA::setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc, ThreadID tid) { switch (misc_reg) { case MISCREG_FPCR: diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh index 36e708450..54e12022a 100644 --- a/src/arch/alpha/isa.hh +++ b/src/arch/alpha/isa.hh @@ -77,10 +77,9 @@ namespace AlphaISA MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const; MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0); - void setMiscRegNoEffect(int misc_reg, const MiscReg &val, - ThreadID tid = 0); - void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc, - ThreadID tid = 0); + void setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid=0); + void setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc, + ThreadID tid=0); void clear() -- cgit v1.2.3