From 390a74f59934b85d91489f8a563450d8321b602d Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 25 Nov 2019 02:26:51 -0800 Subject: sim,arch: Collapse the ISA specific versions of m5Syscall. The x86 version doesn't do anything x86 specific, and so can be used generically in sim/pseudo_inst.(hh|cc) Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I46c2a7d326bd7a95daa8611888051c180e92e446 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23177 Tested-by: kokoro Reviewed-by: Gabe Black Maintainer: Gabe Black --- src/arch/alpha/pseudo_inst.hh | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'src/arch/alpha') diff --git a/src/arch/alpha/pseudo_inst.hh b/src/arch/alpha/pseudo_inst.hh index 9f8b508c2..f15d0f572 100644 --- a/src/arch/alpha/pseudo_inst.hh +++ b/src/arch/alpha/pseudo_inst.hh @@ -32,14 +32,13 @@ #define __ARCH_ALPHA_PSEUDO_INST_HH__ #include "arch/generic/pseudo_inst.hh" -#include "base/logging.hh" -class ThreadContext; +namespace AlphaISA +{ -namespace AlphaISA { - using GenericISA::m5Syscall; - using GenericISA::m5PageFault; -} +using GenericISA::m5PageFault; + +} // namespace AlphaISA #endif // __ARCH_ALPHA_PSEUDO_INST_HH__ -- cgit v1.2.3