From a473b5a6eb269cc303ecfb5e5643d891a5d255d9 Mon Sep 17 00:00:00 2001
From: Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com>
Date: Wed, 5 Apr 2017 13:14:34 -0500
Subject: cpu: Simplify the rename interface and use RegId

With the hierarchical RegId there are a lot of functions that are
redundant now.

The idea behind the simplification is that instead of having the regId,
telling which kind of register read/write/rename/lookup/etc. and then
the function panic_if'ing if the regId is not of the appropriate type,
we provide an interface that decides what kind of register to read
depending on the register type of the given regId.

Change-Id: I7d52e9e21fc01205ae365d86921a4ceb67a57178
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2702
---
 src/arch/alpha/isa.hh         | 3 +++
 src/arch/alpha/isa/branch.isa | 2 +-
 src/arch/alpha/isa/fp.isa     | 2 +-
 src/arch/alpha/isa/main.isa   | 6 +++---
 4 files changed, 8 insertions(+), 5 deletions(-)

(limited to 'src/arch/alpha')

diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index 6c06fc397..80d8ab149 100644
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -38,6 +38,7 @@
 #include "arch/alpha/registers.hh"
 #include "arch/alpha/types.hh"
 #include "base/types.hh"
+#include "cpu/reg_class.hh"
 #include "sim/sim_object.hh"
 #include "sim/system.hh"
 
@@ -95,6 +96,8 @@ namespace AlphaISA
         void serialize(CheckpointOut &cp) const override;
         void unserialize(CheckpointIn &cp) override;
 
+        RegId flattenRegId(const RegId& regId) const { return regId; }
+
         int
         flattenIntIndex(int reg) const
         {
diff --git a/src/arch/alpha/isa/branch.isa b/src/arch/alpha/isa/branch.isa
index d4b6db043..a43efff9c 100644
--- a/src/arch/alpha/isa/branch.isa
+++ b/src/arch/alpha/isa/branch.isa
@@ -130,7 +130,7 @@ output decoder {{
     Jump::branchTarget(ThreadContext *tc) const
     {
         PCState pc = tc->pcState();
-        uint64_t Rb = tc->readIntReg(_srcRegIdx[0].regIdx);
+        uint64_t Rb = tc->readIntReg(_srcRegIdx[0].index());
         pc.set((Rb & ~3) | (pc.pc() & 1));
         return pc;
     }
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index afece988f..6213c8e08 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -149,7 +149,7 @@ output decoder {{
 
 #ifndef SS_COMPATIBLE_DISASSEMBLY
         std::string suffix("");
-        suffix += ((_destRegIdx[0].regClass == FloatRegClass)
+        suffix += ((_destRegIdx[0].isFloatReg())
                    ? fpTrappingModeSuffix[trappingMode]
                    : intTrappingModeSuffix[trappingMode]);
         suffix += roundingModeSuffix[roundingMode];
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index e75cec524..34e2cb5ad 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -246,11 +246,11 @@ output decoder {{
     void
     AlphaStaticInst::printReg(std::ostream &os, RegId reg) const
     {
-        if (reg.regClass == IntRegClass) {
-            ccprintf(os, "r%d", reg.regIdx);
+        if (reg.isIntReg()) {
+            ccprintf(os, "r%d", reg.index());
         }
         else {
-            ccprintf(os, "f%d", reg.regIdx);
+            ccprintf(os, "f%d", reg.index());
         }
     }
 
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