From 12e26c68c3e12a17c29b694012819bc7bae7bb5a Mon Sep 17 00:00:00 2001
From: Kevin Lim <ktlim@umich.edu>
Date: Sun, 12 Nov 2006 20:15:30 -0500
Subject: Updates to support new interrupt processing and removal of PcPAL.

src/arch/alpha/interrupts.hh:
    No need for this now that the ThreadContext is being used to set these IPRs in interrupts.
    Also split up the interrupt checking from the updating of the IPL and interrupt summary.
src/arch/alpha/tlb.cc:
    Check the PC for whether or not it's in PAL mode, not the addr.
src/cpu/o3/alpha/cpu.hh:
    Split up getting the interrupt from actually processing the interrupt.
src/cpu/o3/alpha/cpu_impl.hh:
    Splut up the processing of interrupts.
src/cpu/o3/commit_impl.hh:
    Update for ISA-oriented interrupt changes.
src/cpu/o3/fetch_impl.hh:
    Fix broken if statement from PcPAL updates, and properly populate the request fields.

    Also more debugging output.
src/cpu/ozone/cpu_impl.hh:
    Updates for ISA-oriented interrupt stuff.
src/cpu/ozone/front_end_impl.hh:
    Populate request fields properly.
src/cpu/simple/base.cc:
    Update for interrupt stuff.

--HG--
extra : convert_revision : 9bac3f9ffed4948ee788699b2fa8419bc1ca647c
---
 src/arch/alpha/interrupts.hh | 28 ++++++++++++++++------------
 src/arch/alpha/tlb.cc        |  2 +-
 2 files changed, 17 insertions(+), 13 deletions(-)

(limited to 'src/arch/alpha')

diff --git a/src/arch/alpha/interrupts.hh b/src/arch/alpha/interrupts.hh
index 75031ae47..a86fb2d7b 100644
--- a/src/arch/alpha/interrupts.hh
+++ b/src/arch/alpha/interrupts.hh
@@ -49,6 +49,7 @@ namespace AlphaISA
         {
             memset(interrupts, 0, sizeof(interrupts));
             intstatus = 0;
+            newInfoSet = false;
         }
 
         void post(int int_num, int index)
@@ -137,18 +138,10 @@ namespace AlphaISA
             }
 
             if (ipl && ipl > tc->readMiscReg(IPR_IPLR)) {
-                tc->setMiscReg(IPR_ISR, summary);
-                tc->setMiscReg(IPR_INTID, ipl);
-
-        /* The following needs to be added back in somehow */
-        // Checker needs to know these two registers were updated.
-/*#if USE_CHECKER
-        if (this->checker) {
-            this->checker->threadBase()->setMiscReg(IPR_ISR, summary);
-            this->checker->threadBase()->setMiscReg(IPR_INTID, ipl);
-        }
-#endif*/
-
+//                assert(!newInfoSet);
+                newIpl = ipl;
+                newSummary = newSummary;
+                newInfoSet = true;
                 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
                         tc->readMiscReg(IPR_IPLR), ipl, summary);
 
@@ -158,7 +151,18 @@ namespace AlphaISA
             }
         }
 
+        void updateIntrInfo(ThreadContext *tc)
+        {
+            assert(newInfoSet);
+            tc->setMiscReg(IPR_ISR, newSummary);
+            tc->setMiscReg(IPR_INTID, newIpl);
+            newInfoSet = false;
+        }
+
       private:
+        bool newInfoSet;
+        int newIpl;
+        int newSummary;
     };
 }
 
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index ae302e686..af69e45c0 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -292,7 +292,7 @@ namespace AlphaISA
     Fault
     ITB::translate(RequestPtr &req, ThreadContext *tc) const
     {
-        if (PcPAL(req->getVaddr())) {
+        if (PcPAL(req->getPC())) {
             // strip off PAL PC marker (lsb is 1)
             req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
             hits++;
-- 
cgit v1.2.3


From 0f633c5fee2a371bc216ca71192c6ff02dcc3b5c Mon Sep 17 00:00:00 2001
From: Steve Reinhardt <stever@eecs.umich.edu>
Date: Sun, 12 Nov 2006 22:03:42 -0800
Subject: Make setRegWithEffect do something in SE mode.

--HG--
extra : convert_revision : 88fdaa403fe6d083f8c8fc064cb0d0d6a8b8daf8
---
 src/arch/alpha/miscregfile.cc | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'src/arch/alpha')

diff --git a/src/arch/alpha/miscregfile.cc b/src/arch/alpha/miscregfile.cc
index 4cf57a690..962d4609f 100644
--- a/src/arch/alpha/miscregfile.cc
+++ b/src/arch/alpha/miscregfile.cc
@@ -132,7 +132,6 @@ namespace AlphaISA
     MiscRegFile::setRegWithEffect(int misc_reg, const MiscReg &val,
             ThreadContext *tc)
     {
-#if FULL_SYSTEM
         switch(misc_reg) {
           case MISCREG_FPCR:
             fpcr = val;
@@ -150,12 +149,13 @@ namespace AlphaISA
             intr_flag = val;
             return;
           default:
-            return setIpr(misc_reg, val, tc);
-        }
+#if FULL_SYSTEM
+            setIpr(misc_reg, val, tc);
 #else
-        //panic("No registers with side effects in SE mode!");
-        return;
+            panic("No registers with side effects in SE mode!");
 #endif
+            return;
+        }
     }
 
 }
-- 
cgit v1.2.3