From ae390c629f2a10fd6a1c2eb50b7d3510d6e091da Mon Sep 17 00:00:00 2001
From: Gabe Black <gabeblack@google.com>
Date: Mon, 2 Sep 2019 21:26:12 -0700
Subject: arch: Make a base class for Interrupts.

That abstracts the ISA further from the CPU, getting us a small step
closer to being able to build in more than one ISA at a time.

Change-Id: Ibf7e26a3df411ffe994ac1e11d2a53b656863223
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20831
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
---
 src/arch/alpha/AlphaInterrupts.py | 4 ++--
 src/arch/alpha/interrupts.hh      | 6 +++---
 src/arch/alpha/isa/decoder.isa    | 2 +-
 3 files changed, 6 insertions(+), 6 deletions(-)

(limited to 'src/arch/alpha')

diff --git a/src/arch/alpha/AlphaInterrupts.py b/src/arch/alpha/AlphaInterrupts.py
index a75b11fc0..7bab9b0ca 100644
--- a/src/arch/alpha/AlphaInterrupts.py
+++ b/src/arch/alpha/AlphaInterrupts.py
@@ -26,9 +26,9 @@
 #
 # Authors: Gabe Black
 
-from m5.SimObject import SimObject
+from m5.objects.BaseInterrupts import BaseInterrupts
 
-class AlphaInterrupts(SimObject):
+class AlphaInterrupts(BaseInterrupts):
     type = 'AlphaInterrupts'
     cxx_class = 'AlphaISA::Interrupts'
     cxx_header = "arch/alpha/interrupts.hh"
diff --git a/src/arch/alpha/interrupts.hh b/src/arch/alpha/interrupts.hh
index 61ac6c968..e054b4389 100644
--- a/src/arch/alpha/interrupts.hh
+++ b/src/arch/alpha/interrupts.hh
@@ -36,17 +36,17 @@
 
 #include "arch/alpha/faults.hh"
 #include "arch/alpha/isa_traits.hh"
+#include "arch/generic/interrupts.hh"
 #include "base/compiler.hh"
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
 #include "debug/Flow.hh"
 #include "debug/Interrupt.hh"
 #include "params/AlphaInterrupts.hh"
-#include "sim/sim_object.hh"
 
 namespace AlphaISA {
 
-class Interrupts : public SimObject
+class Interrupts : public BaseInterrupts
 {
   private:
     bool newInfoSet;
@@ -67,7 +67,7 @@ class Interrupts : public SimObject
         return dynamic_cast<const Params *>(_params);
     }
 
-    Interrupts(Params * p) : SimObject(p), cpu(NULL)
+    Interrupts(Params * p) : BaseInterrupts(p), cpu(NULL)
     {
         memset(interrupts, 0, sizeof(interrupts));
         intstatus = 0;
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 8732d70ba..020e43359 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -982,7 +982,7 @@ decode OPCODE default Unknown::unknown() {
             }}, IsNonSpeculative);
             0x01: quiesce({{
                 // Don't sleep if (unmasked) interrupts are pending
-                Interrupts* interrupts =
+                BaseInterrupts* interrupts =
                     xc->tcBase()->getCpuPtr()->getInterruptController(0);
                 if (interrupts->checkInterrupts(xc->tcBase())) {
                     PseudoInst::quiesceSkip(xc->tcBase());
-- 
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