From ec26f0bb3d3d0af9dc87e5e3f25c2b90f2db0332 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 11 Aug 2006 20:21:35 -0400 Subject: Started adding a system to output data after every instruction. src/arch/alpha/regfile.hh: src/arch/mips/regfile/float_regfile.hh: src/arch/mips/regfile/int_regfile.hh: src/arch/mips/regfile/misc_regfile.hh: src/cpu/exetrace.hh: Added functions to start to support dumping register values once per cycle. src/cpu/exetrace.cc: Added some code to support printing the value of registers after each cycle. src/python/m5/main.py: Options to turn on output after every instruction. They are commented out. --HG-- extra : convert_revision : 168a48a6b98ab6be412a96bdee831c71906958b0 --- src/arch/alpha/regfile.hh | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'src/arch/alpha') diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh index c31619408..43b48a0ab 100644 --- a/src/arch/alpha/regfile.hh +++ b/src/arch/alpha/regfile.hh @@ -45,6 +45,21 @@ class ThreadContext; namespace AlphaISA { + static inline std::string getIntRegName(RegIndex) + { + return ""; + } + + static inline std::string getFloatRegName(RegIndex) + { + return ""; + } + + static inline std::string getMiscRegName(RegIndex) + { + return ""; + } + class IntRegFile { protected: -- cgit v1.2.3