From f54020eb8155371725ab75b0fc5c419287eca084 Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Mon, 4 Jun 2018 09:40:19 +0100
Subject: misc: Using smart pointers for memory Requests

This patch is changing the underlying type for RequestPtr from Request*
to shared_ptr<Request>. Having memory requests being managed by smart
pointers will simplify the code; it will also prevent memory leakage and
dangling pointers.

Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10996
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
---
 src/arch/alpha/locked_mem.hh |  4 ++--
 src/arch/alpha/tlb.cc        | 13 +++++++------
 src/arch/alpha/tlb.hh        | 13 +++++++------
 3 files changed, 16 insertions(+), 14 deletions(-)

(limited to 'src/arch/alpha')

diff --git a/src/arch/alpha/locked_mem.hh b/src/arch/alpha/locked_mem.hh
index a71a24cfb..0fa6782a8 100644
--- a/src/arch/alpha/locked_mem.hh
+++ b/src/arch/alpha/locked_mem.hh
@@ -85,7 +85,7 @@ handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
 
 template <class XC>
 inline void
-handleLockedRead(XC *xc, RequestPtr req)
+handleLockedRead(XC *xc, const RequestPtr &req)
 {
     xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
     xc->setMiscReg(MISCREG_LOCKFLAG, true);
@@ -99,7 +99,7 @@ handleLockedSnoopHit(XC *xc)
 
 template <class XC>
 inline bool
-handleLockedWrite(XC *xc, RequestPtr req, Addr cacheBlockMask)
+handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
 {
     if (req->isUncacheable()) {
         // Funky Turbolaser mailbox access...don't update
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index f77c45854..949c2e665 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -203,7 +203,7 @@ TLB::lookup(Addr vpn, uint8_t asn)
 }
 
 Fault
-TLB::checkCacheability(RequestPtr &req, bool itb)
+TLB::checkCacheability(const RequestPtr &req, bool itb)
 {
     // in Alpha, cacheability is controlled by upper-level bits of the
     // physical address
@@ -372,7 +372,7 @@ TLB::unserialize(CheckpointIn &cp)
 }
 
 Fault
-TLB::translateInst(RequestPtr req, ThreadContext *tc)
+TLB::translateInst(const RequestPtr &req, ThreadContext *tc)
 {
     //If this is a pal pc, then set PHYSICAL
     if (FullSystem && PcPAL(req->getPC()))
@@ -449,7 +449,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
 }
 
 Fault
-TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
+TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
 {
     mode_type mode =
         (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM));
@@ -599,7 +599,7 @@ TLB::index(bool advance)
 }
 
 Fault
-TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
+TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
 {
     if (mode == Execute)
         return translateInst(req, tc);
@@ -608,7 +608,7 @@ TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
 }
 
 void
-TLB::translateTiming(RequestPtr req, ThreadContext *tc,
+TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
         Translation *translation, Mode mode)
 {
     assert(translation);
@@ -616,7 +616,8 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
 }
 
 Fault
-TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
+TLB::finalizePhysical(const RequestPtr &req, ThreadContext *tc,
+                      Mode mode) const
 {
     return NoFault;
 }
diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index 08166bc6e..e28f260ea 100644
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -114,7 +114,7 @@ class TLB : public BaseTLB
         return unimplBits == 0 || unimplBits == VAddrUnImplMask;
     }
 
-    static Fault checkCacheability(RequestPtr &req, bool itb = false);
+    static Fault checkCacheability(const RequestPtr &req, bool itb = false);
 
     // Checkpointing
     void serialize(CheckpointOut &cp) const override;
@@ -137,17 +137,18 @@ class TLB : public BaseTLB
     }
 
   protected:
-    Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
-    Fault translateInst(RequestPtr req, ThreadContext *tc);
+    Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
+    Fault translateInst(const RequestPtr &req, ThreadContext *tc);
 
   public:
     Fault translateAtomic(
-            RequestPtr req, ThreadContext *tc, Mode mode) override;
+            const RequestPtr &req, ThreadContext *tc, Mode mode) override;
     void translateTiming(
-            RequestPtr req, ThreadContext *tc,
+            const RequestPtr &req, ThreadContext *tc,
             Translation *translation, Mode mode) override;
     Fault finalizePhysical(
-            RequestPtr req, ThreadContext *tc, Mode mode) const override;
+            const RequestPtr &req, ThreadContext *tc,
+            Mode mode) const override;
 };
 
 } // namespace AlphaISA
-- 
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