From f6742ea26e1a1cac21b486c7c5adad6fb6304e92 Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Sun, 25 Jan 2015 07:22:26 -0500
Subject: cpu: Remove all notion that we know when the cpu is misspeculating.

We have no way of knowing if a CPU model is on the wrong path with
our execute-in-execute CPU models. Don't pretend that we do.
---
 src/arch/alpha/ev5.cc    | 12 +++---------
 src/arch/alpha/faults.cc | 11 ++++-------
 2 files changed, 7 insertions(+), 16 deletions(-)

(limited to 'src/arch/alpha')

diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index d66ab42aa..d45786a83 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -161,8 +161,7 @@ ISA::readIpr(int idx, ThreadContext *tc)
 
       case IPR_DTB_PTE:
         {
-            TlbEntry &entry
-                = tc->getDTBPtr()->index(!tc->misspeculating());
+            TlbEntry &entry = tc->getDTBPtr()->index(1);
 
             retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32;
             retval |= ((uint64_t)entry.xre & ULL(0xf)) << 8;
@@ -202,9 +201,6 @@ int break_ipl = -1;
 void
 ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
 {
-    if (tc->misspeculating())
-        return;
-
     switch (idx) {
       case IPR_PALtemp0:
       case IPR_PALtemp1:
@@ -484,10 +480,8 @@ SimpleThread::hwrei()
 
     CPA::cpa()->swAutoBegin(tc, pc.npc());
 
-    if (!misspeculating()) {
-        if (kernelStats)
-            kernelStats->hwrei();
-    }
+    if (kernelStats)
+        kernelStats->hwrei();
 
     // FIXME: XXX check for interrupts? XXX
     return NoFault;
diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index 6375b0bfb..2928f8d65 100644
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -147,8 +147,7 @@ DtbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
         // on VPTE loads (instead of locking the registers until IPR_VA is
         // read, like the EV5).  The EV6 approach is cleaner and seems to
         // work with EV5 PAL code, but not the other way around.
-        if (!tc->misspeculating() &&
-            reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
+        if (reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
             // set VA register with faulting address
             tc->setMiscRegNoEffect(IPR_VA, vaddr);
 
@@ -172,11 +171,9 @@ void
 ItbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
 {
     if (FullSystem) {
-        if (!tc->misspeculating()) {
-            tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
-            tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
-                tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
-        }
+        tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
+        tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
+            tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
     }
 
     AlphaFault::invoke(tc);
-- 
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