From f65c190d0b0185ca2965d09149f33cb78555a1bf Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Tue, 16 Feb 2016 13:21:04 -0600 Subject: arm: Add support for memory-mapped m5ops Add support for a memory mapped m5op interface. When enabled, the TLB intercepts accesses in the 64KiB region designated by the ArmTLB.m5ops_base parameter. An access to this range maps to a specific m5op call. The upper 8 bits of the offset into the range denote the m5op function to call and the lower 8 bits denote the subfunction. Change-Id: I55fd8ac1afef4c3cc423b973870c9fe600a843a2 Signed-off-by: Andreas Sandberg Reviewed-by: Nikos Nikoleris Reviewed-on: https://gem5-review.googlesource.com/2964 --- src/arch/arm/ArmTLB.py | 1 + 1 file changed, 1 insertion(+) (limited to 'src/arch/arm/ArmTLB.py') diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py index 4e6c69f72..b3f711d83 100644 --- a/src/arch/arm/ArmTLB.py +++ b/src/arch/arm/ArmTLB.py @@ -63,6 +63,7 @@ class ArmTLB(SimObject): type = 'ArmTLB' cxx_class = 'ArmISA::TLB' cxx_header = "arch/arm/tlb.hh" + sys = Param.System(Parent.any, "system object parameter") size = Param.Int(64, "TLB size") walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker") is_stage2 = Param.Bool(False, "Is this a stage 2 TLB?") -- cgit v1.2.3