From 0cba96ba6a5d7a4dab2a63b14149c49dfbfbb3bc Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 26 May 2012 13:44:46 -0700 Subject: CPU: Merge the predecoder and decoder. These classes are always used together, and merging them will give the ISAs more flexibility in how they cache things and manage the process. --HG-- rename : src/arch/x86/predecoder_tables.cc => src/arch/x86/decoder_tables.cc --- src/arch/arm/SConscript | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src/arch/arm/SConscript') diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript index 0f94455bd..44b6286a0 100644 --- a/src/arch/arm/SConscript +++ b/src/arch/arm/SConscript @@ -62,7 +62,6 @@ if env['TARGET_ISA'] == 'arm': Source('linux/system.cc') Source('miscregs.cc') Source('nativetrace.cc') - Source('predecoder.cc') Source('process.cc') Source('remote_gdb.cc') Source('stacktrace.cc') @@ -78,9 +77,9 @@ if env['TARGET_ISA'] == 'arm': SimObject('ArmTLB.py') DebugFlag('Arm') - DebugFlag('TLBVerbose') + DebugFlag('Decoder', "Instructions returned by the predecoder") DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi") - DebugFlag('Predecoder', "Instructions returned by the predecoder") + DebugFlag('TLBVerbose') # Add in files generated by the ISA description. isa_desc_files = env.ISADesc('isa/main.isa') -- cgit v1.2.3