From 0f024be0ca5bd9830f8fd84456894c965cc7c16c Mon Sep 17 00:00:00 2001 From: Ciro Santilli Date: Fri, 21 Dec 2018 14:25:24 +0000 Subject: arch-arm: implement the GDB XML target description for ARM The supported registers are essentially the same as before this patch, but it is now trivial to make new registers visible in future commits. Change-Id: Id15b7aeccca824c342e49a626d2877179474f3d4 Reviewed-on: https://gem5-review.googlesource.com/c/15138 Reviewed-by: Andreas Sandberg Reviewed-by: Gabe Black Maintainer: Andreas Sandberg --- src/arch/arm/SConscript | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/arch/arm/SConscript') diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript index c84c69ba6..a1063f039 100644 --- a/src/arch/arm/SConscript +++ b/src/arch/arm/SConscript @@ -105,3 +105,10 @@ if env['TARGET_ISA'] == 'arm': # Add files generated by the ISA description. ISADesc('isa/main.isa', decoder_splits=3, exec_splits=6) + + GdbXml('arm/arm-with-neon.xml', 'gdb_xml_arm_target') + GdbXml('arm/arm-core.xml', 'gdb_xml_arm_core') + GdbXml('arm/arm-vfpv3.xml', 'gdb_xml_arm_vfpv3') + GdbXml('aarch64.xml', 'gdb_xml_aarch64_target') + GdbXml('aarch64-core.xml', 'gdb_xml_aarch64_core') + GdbXml('aarch64-fpu.xml', 'gdb_xml_aarch64_fpu') -- cgit v1.2.3