From 2178859b76bb13b1d225fc4dffa04d43d2db2e14 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 13 May 2011 17:27:01 -0500 Subject: ARM: Break up condition codes into normal flags, saturation, and simd. This change splits out the condcodes from being one monolithic register into three blocks that are updated independently. This allows CPUs to not have to do RMW operations on the flags registers for instructions that don't write all flags. --- src/arch/arm/faults.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/arch/arm/faults.cc') diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index 03a65ea88..4b58a7144 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -107,7 +107,9 @@ ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst) SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) | - tc->readIntReg(INTREG_CONDCODES); + tc->readIntReg(INTREG_CONDCODES_F) | + tc->readIntReg(INTREG_CONDCODES_Q) | + tc->readIntReg(INTREG_CONDCODES_GE); Addr curPc M5_VAR_USED = tc->pcState().pc(); ITSTATE it = tc->pcState().itstate(); saved_cpsr.it2 = it.top6; -- cgit v1.2.3