From 401165c778108ab22aeeee55c4f4451ca93bcffb Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 13 May 2011 17:27:01 -0500 Subject: ARM: Further break up condition code into NZ, C, V bits. Break up the condition code bits into NZ, C, V registers. These are individually written and this removes some incorrect dependencies between instructions. --- src/arch/arm/faults.cc | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'src/arch/arm/faults.cc') diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index e7e78e178..7dd81a681 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -106,9 +106,12 @@ ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst) SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); - CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) | - tc->readIntReg(INTREG_CONDCODES_F) | - tc->readIntReg(INTREG_CONDCODES_GE); + CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR); + saved_cpsr.nz = tc->readIntReg(INTREG_CONDCODES_NZ); + saved_cpsr.c = tc->readIntReg(INTREG_CONDCODES_C); + saved_cpsr.v = tc->readIntReg(INTREG_CONDCODES_V); + saved_cpsr.ge = tc->readIntReg(INTREG_CONDCODES_GE); + Addr curPc M5_VAR_USED = tc->pcState().pc(); ITSTATE it = tc->pcState().itstate(); saved_cpsr.it2 = it.top6; -- cgit v1.2.3