From 72ecef7a759f10b4816ecf13a1289fc6d9443c92 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Fri, 9 Feb 2018 10:01:39 +0000 Subject: arch-arm: Fix FSC generation in AbortFault The fault status code generated by a Prefetch/Data Fault was containing a wrong value when the fault was triggered in aarch32 but handled in aarch64. This because the encoding differs between the two ISAs and the encoder was just checking the starting ISA rather than the the ending one. In this case the getFsr must be called after we know which is the ending ISA, which happens only after ArmFault::invoke gets called. The fsc update hence happens before writing into the Syndrome register. Change-Id: I725f12b6dcc0178f608233bd3d15e466d1cd1ffc Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/8362 Maintainer: Andreas Sandberg --- src/arch/arm/faults.cc | 65 +++++++++++++++++++++++++++++++++++++------------- 1 file changed, 48 insertions(+), 17 deletions(-) (limited to 'src/arch/arm/faults.cc') diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index 310545bc3..a1952d664 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -1032,13 +1032,13 @@ AbortFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) } // Get effective fault source encoding CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); - FSR fsr = getFsr(tc); // source must be determined BEFORE invoking generic routines which will // try to set hsr etc. and are based upon source! ArmFaultVals::invoke(tc, inst); if (!this->to64) { // AArch32 + FSR fsr = getFsr(tc); if (cpsr.mode == MODE_HYP) { tc->setMiscReg(T::HFarIndex, faultAddr); } else if (stage2) { @@ -1068,33 +1068,64 @@ AbortFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) } template -FSR -AbortFault::getFsr(ThreadContext *tc) +void +AbortFault::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) { - FSR fsr = 0; + srcEncoded = getFaultStatusCode(tc); + if (srcEncoded == ArmFault::FaultSourceInvalid) { + panic("Invalid fault source\n"); + } + ArmFault::setSyndrome(tc, syndrome_reg); +} - if (((CPSR) tc->readMiscRegNoEffect(MISCREG_CPSR)).width) { +template +uint8_t +AbortFault::getFaultStatusCode(ThreadContext *tc) const +{ + + panic_if(!this->faultUpdated, + "Trying to use un-updated ArmFault internal variables\n"); + + uint8_t fsc = 0; + + if (!this->to64) { // AArch32 assert(tranMethod != ArmFault::UnknownTran); if (tranMethod == ArmFault::LpaeTran) { - srcEncoded = ArmFault::longDescFaultSources[source]; - fsr.status = srcEncoded; - fsr.lpae = 1; + fsc = ArmFault::longDescFaultSources[source]; } else { - srcEncoded = ArmFault::shortDescFaultSources[source]; - fsr.fsLow = bits(srcEncoded, 3, 0); - fsr.fsHigh = bits(srcEncoded, 4); - fsr.domain = static_cast(domain); + fsc = ArmFault::shortDescFaultSources[source]; } - fsr.wnr = (write ? 1 : 0); - fsr.ext = 0; } else { // AArch64 - srcEncoded = ArmFault::aarch64FaultSources[source]; + fsc = ArmFault::aarch64FaultSources[source]; } - if (srcEncoded == ArmFault::FaultSourceInvalid) { - panic("Invalid fault source\n"); + + return fsc; +} + +template +FSR +AbortFault::getFsr(ThreadContext *tc) const +{ + FSR fsr = 0; + + auto fsc = getFaultStatusCode(tc); + + // AArch32 + assert(tranMethod != ArmFault::UnknownTran); + if (tranMethod == ArmFault::LpaeTran) { + fsr.status = fsc; + fsr.lpae = 1; + } else { + fsr.fsLow = bits(fsc, 3, 0); + fsr.fsHigh = bits(fsc, 4); + fsr.domain = static_cast(domain); } + + fsr.wnr = (write ? 1 : 0); + fsr.ext = 0; + return fsr; } -- cgit v1.2.3