From 649c239ceef2d107fae253b1008c6f214f242d73 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 13 Sep 2011 12:58:08 -0400 Subject: LSQ: Only trigger a memory violation with a load/load if the value changes. Only create a memory ordering violation when the value could have changed between two subsequent loads, instead of just when loads go out-of-order to the same address. While not very common in the case of Alpha, with an architecture with a hardware table walker this can happen reasonably frequently beacuse a translation will miss and start a table walk and before the CPU re-schedules the faulting instruction another one will pass it to the same address (or cache block depending on the dendency checking). This patch has been tested with a couple of self-checking hand crafted programs to stress ordering between two cores. The performance improvement on SPEC benchmarks can be substantial (2-10%). --- src/arch/arm/faults.hh | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'src/arch/arm/faults.hh') diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh index 54edb336b..fe1258a16 100644 --- a/src/arch/arm/faults.hh +++ b/src/arch/arm/faults.hh @@ -242,16 +242,6 @@ class FlushPipe : public ArmFaultVals StaticInstPtr inst = StaticInst::nullStaticInstPtr); }; -// A fault that flushes the pipe, including the faulting instructions -class ReExec : public ArmFaultVals -{ - public: - ReExec() {} - void invoke(ThreadContext *tc, - StaticInstPtr inst = StaticInst::nullStaticInstPtr); -}; - - static inline Fault genMachineCheckFault() { return new Reset(); -- cgit v1.2.3