From 6fa49382ef22e1b01fb24503e3bbe5ab3556750a Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Wed, 31 Oct 2018 17:12:30 +0000 Subject: arch-arm: ArmSystem::resetAddr64 renamed to be used in AArch32 ARMv8 differs from ARMv7 with the presence of RVBAR register, which contains the implementation defined reset address when EL3 is not implemented. The entry 0x0 in the AArch32 vector table, once used for the Reset Vector, is now marked as "Not used", stating that it is now IMPLEMENTATION DEFINED. An implementation might still use this vector table entry to hold the Reset vector, but having a Reset address != than the general vector table (for any other exception) is allowed. At the moment any Reset exception is still using 0 as a vector table base address. This patch is extending the ArmSystem::resetAddr64 to ArmSystem::resetAddr so that it can be used for initializing MVBAR/RVBAR. In order to do so, we are providing a specialized behavior for the Reset exception when evaluating the vector base address. Change-Id: I051a730dc089e194db3b107bbed19251c661f87e Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/14000 Maintainer: Andreas Sandberg --- src/arch/arm/faults.hh | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/arch/arm/faults.hh') diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh index 90b550198..dcda03b5f 100644 --- a/src/arch/arm/faults.hh +++ b/src/arch/arm/faults.hh @@ -81,7 +81,7 @@ class ArmFault : public FaultBase bool hypRouted; // True if the fault has been routed to Hypervisor - Addr getVector(ThreadContext *tc); + virtual Addr getVector(ThreadContext *tc); Addr getVector64(ThreadContext *tc); public: @@ -269,6 +269,9 @@ class ArmFaultVals : public ArmFault class Reset : public ArmFaultVals { + protected: + Addr getVector(ThreadContext *tc) override; + public: void invoke(ThreadContext *tc, const StaticInstPtr &inst = StaticInst::nullStaticInstPtr) override; -- cgit v1.2.3