From acd148a76c29a6e647dc2cc15ef17667c61f8de6 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Thu, 12 Sep 2019 10:23:16 +0100 Subject: arch-arm: Set CM bit in DataAbort The CM bit in a DataAbort ISS indicates whether the Data Abort came from a cache maintenance or address translation instruction. Change-Id: I8888520446550581c8dd0507a8989935db7047be Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21305 Maintainer: Andreas Sandberg Tested-by: kokoro --- src/arch/arm/faults.hh | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/arch/arm/faults.hh') diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh index 5e68875f5..645a461fe 100644 --- a/src/arch/arm/faults.hh +++ b/src/arch/arm/faults.hh @@ -136,6 +136,7 @@ class ArmFault : public FaultBase SAS, // DataAbort: Syndrome Access Size SSE, // DataAbort: Syndrome Sign Extend SRT, // DataAbort: Syndrome Register Transfer + CM, // DataAbort: Cache Maintenance/Address Translation Op // AArch64 only SF, // DataAbort: width of the accessed register is SixtyFour @@ -482,6 +483,7 @@ class DataAbort : public AbortFault uint8_t sas; uint8_t sse; uint8_t srt; + uint8_t cm; // AArch64 only bool sf; @@ -491,7 +493,7 @@ class DataAbort : public AbortFault bool _stage2 = false, ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : AbortFault(_addr, _write, _domain, _source, _stage2, _tranMethod), - isv(false), sas (0), sse(0), srt(0), sf(false), ar(false) + isv(false), sas (0), sse(0), srt(0), cm(0), sf(false), ar(false) {} ExceptionClass ec(ThreadContext *tc) const override; -- cgit v1.2.3