From 5e8287d2e2eaf058495442ea9e32fafc343a0b53 Mon Sep 17 00:00:00 2001 From: Nathanael Premillieu Date: Wed, 5 Apr 2017 12:46:06 -0500 Subject: arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/2700 --- src/arch/arm/insts/branch64.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/arch/arm/insts/branch64.cc') diff --git a/src/arch/arm/insts/branch64.cc b/src/arch/arm/insts/branch64.cc index 49ba3402a..d0a4f2924 100644 --- a/src/arch/arm/insts/branch64.cc +++ b/src/arch/arm/insts/branch64.cc @@ -95,7 +95,7 @@ BranchReg64::generateDisassembly( { std::stringstream ss; printMnemonic(ss, "", false); - printReg(ss, op1); + printIntReg(ss, op1); return ss.str(); } @@ -106,7 +106,7 @@ BranchRet64::generateDisassembly( std::stringstream ss; printMnemonic(ss, "", false); if (op1 != INTREG_X30) - printReg(ss, op1); + printIntReg(ss, op1); return ss.str(); } @@ -125,7 +125,7 @@ BranchImmReg64::generateDisassembly( { std::stringstream ss; printMnemonic(ss, "", false); - printReg(ss, op1); + printIntReg(ss, op1); ccprintf(ss, ", "); printTarget(ss, pc + imm, symtab); return ss.str(); @@ -137,7 +137,7 @@ BranchImmImmReg64::generateDisassembly( { std::stringstream ss; printMnemonic(ss, "", false); - printReg(ss, op1); + printIntReg(ss, op1); ccprintf(ss, ", #%#x, ", imm1); printTarget(ss, pc + imm2, symtab); return ss.str(); -- cgit v1.2.3