From 4d8f4db8d135a23ceb5d54d3096e0598dd31e2fe Mon Sep 17 00:00:00 2001
From: Gene WU <gene.wu@arm.com>
Date: Wed, 25 Aug 2010 19:10:42 -0500
Subject: ARM: Use fewer micro-ops for register update loads if possible.

Allow some loads that update the base register to use just two micro-ops. three
micro-ops are only used if the destination register matches the offset register
or the PC is the destination regsiter. If the PC is updated it needs to be
the last micro-op otherwise O3 will mispredict.
---
 src/arch/arm/insts/macromem.cc | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

(limited to 'src/arch/arm/insts/macromem.cc')

diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc
index 5602231f9..f64fbeff9 100644
--- a/src/arch/arm/insts/macromem.cc
+++ b/src/arch/arm/insts/macromem.cc
@@ -185,7 +185,7 @@ VldMultOp::VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
     if (wb) {
         if (rm != 15 && rm != 13) {
             microOps[uopIdx++] =
-                new MicroAddUop(machInst, rn, rn, rm);
+                new MicroAddUop(machInst, rn, rn, rm, 0, ArmISA::LSL);
         } else {
             microOps[uopIdx++] =
                 new MicroAddiUop(machInst, rn, rn, regs * 8);
@@ -320,7 +320,7 @@ VldSingleOp::VldSingleOp(const char *mnem, ExtMachInst machInst,
     if (wb) {
         if (rm != 15 && rm != 13) {
             microOps[uopIdx++] =
-                new MicroAddUop(machInst, rn, rn, rm);
+                new MicroAddUop(machInst, rn, rn, rm, 0, ArmISA::LSL);
         } else {
             microOps[uopIdx++] =
                 new MicroAddiUop(machInst, rn, rn, loadSize);
@@ -566,7 +566,7 @@ VstMultOp::VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
     if (wb) {
         if (rm != 15 && rm != 13) {
             microOps[uopIdx++] =
-                new MicroAddUop(machInst, rn, rn, rm);
+                new MicroAddUop(machInst, rn, rn, rm, 0, ArmISA::LSL);
         } else {
             microOps[uopIdx++] =
                 new MicroAddiUop(machInst, rn, rn, regs * 8);
@@ -762,7 +762,7 @@ VstSingleOp::VstSingleOp(const char *mnem, ExtMachInst machInst,
     if (wb) {
         if (rm != 15 && rm != 13) {
             microOps[uopIdx++] =
-                new MicroAddUop(machInst, rn, rn, rm);
+                new MicroAddUop(machInst, rn, rn, rm, 0, ArmISA::LSL);
         } else {
             microOps[uopIdx++] =
                 new MicroAddiUop(machInst, rn, rn, storeSize);
@@ -877,6 +877,17 @@ MicroIntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
     return ss.str();
 }
 
+std::string
+MicroIntMov::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+    printMnemonic(ss);
+    printReg(ss, ura);
+    ss << ", ";
+    printReg(ss, urb);
+    return ss.str();
+}
+
 std::string
 MicroIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
-- 
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