From 51aba755390f96a7f1d997b1849bd47072823dea Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Fri, 18 Jan 2019 17:14:56 +0000 Subject: arch-arm: Remove SWP and SWPB instructions The SWP and SWPB instructions have been removed from AArch32. It was previously (ARMv7) possible to enable them with the ID_ISAR0.Swap bits, which are now hardcoded to 0b0000 (SWP and SWPB not implemented) Change-Id: Ic32b534454a7e0f7494a6f0b5e11182c65b3fe24 Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/15815 Maintainer: Andreas Sandberg --- src/arch/arm/insts/mem.cc | 14 -------------- 1 file changed, 14 deletions(-) (limited to 'src/arch/arm/insts/mem.cc') diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc index 3b57aae64..9cc9af025 100644 --- a/src/arch/arm/insts/mem.cc +++ b/src/arch/arm/insts/mem.cc @@ -77,20 +77,6 @@ MemoryReg::printOffset(std::ostream &os) const } } -string -Swap::generateDisassembly(Addr pc, const SymbolTable *symtab) const -{ - stringstream ss; - printMnemonic(ss); - printIntReg(ss, dest); - ss << ", "; - printIntReg(ss, op1); - ss << ", ["; - printIntReg(ss, base); - ss << "]"; - return ss.str(); -} - string RfeOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { -- cgit v1.2.3