From dbee6e0c5406200066b8185fd38fa47dae7cdd2f Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 2 Jun 2010 12:58:11 -0500
Subject: ARM: Add a base class for SRS.

---
 src/arch/arm/insts/mem.hh | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

(limited to 'src/arch/arm/insts/mem.hh')

diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh
index ae3437120..50f718b99 100644
--- a/src/arch/arm/insts/mem.hh
+++ b/src/arch/arm/insts/mem.hh
@@ -87,6 +87,30 @@ class RfeOp : public PredOp
     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 };
 
+// The address is a base register plus an immediate.
+class SrsOp : public PredOp
+{
+  public:
+    enum AddrMode {
+        DecrementAfter,
+        DecrementBefore,
+        IncrementAfter,
+        IncrementBefore
+    };
+  protected:
+    uint32_t regMode;
+    AddrMode mode;
+    bool wb;
+
+    SrsOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+          uint32_t _regMode, AddrMode _mode, bool _wb)
+        : PredOp(mnem, _machInst, __opClass),
+          regMode(_regMode), mode(_mode), wb(_wb)
+    {}
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
 class Memory : public PredOp
 {
   public:
-- 
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