From b1158e493843066acdba153c89573273f5d0fd73 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 2 Jun 2010 12:58:08 -0500
Subject: ARM: Add a register, immediate, immediate to register base for
 [su]bfx.

---
 src/arch/arm/insts/misc.hh | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

(limited to 'src/arch/arm/insts/misc.hh')

diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh
index 7ee2d95f9..b5a75d20d 100644
--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -176,6 +176,24 @@ class RegRegRegOp : public PredOp
     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 };
 
+class RegRegImmImmOp : public PredOp
+{
+  protected:
+    IntRegIndex dest;
+    IntRegIndex op1;
+    uint32_t imm1;
+    uint32_t imm2;
+
+    RegRegImmImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+                   IntRegIndex _dest, IntRegIndex _op1,
+                   uint32_t _imm1, uint32_t _imm2) :
+        PredOp(mnem, _machInst, __opClass),
+        dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2)
+    {}
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
 class RegImmRegShiftOp : public PredOp
 {
   protected:
-- 
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