From 2fb8d481ab37db60a27126d151be23fad10adc50 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 8 Jul 2009 23:02:19 -0700
Subject: ARM: Tune up predicated instruction decoding.

---
 src/arch/arm/insts/pred_inst.cc | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

(limited to 'src/arch/arm/insts/pred_inst.cc')

diff --git a/src/arch/arm/insts/pred_inst.cc b/src/arch/arm/insts/pred_inst.cc
index 539cfc2d2..f98db1c8e 100644
--- a/src/arch/arm/insts/pred_inst.cc
+++ b/src/arch/arm/insts/pred_inst.cc
@@ -32,10 +32,18 @@
 namespace ArmISA
 {
 std::string
-PredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+PredIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
-    printDataInst(ss);
+    printDataInst(ss, false);
+    return ss.str();
+}
+
+std::string
+PredImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+    printDataInst(ss, true);
     return ss.str();
 }
 
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