From 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 Mon Sep 17 00:00:00 2001
From: Yasuko Eckert <yasuko.eckert@amd.com>
Date: Tue, 15 Oct 2013 14:22:44 -0400
Subject: cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
---
 src/arch/arm/insts/static_inst.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/arch/arm/insts/static_inst.cc')

diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc
index 3ab7dfb0e..2a8dee162 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -239,6 +239,8 @@ ArmStaticInst::printReg(std::ostream &os, int reg) const
         assert(rel_reg < NUM_MISCREGS);
         ccprintf(os, "%s", ArmISA::miscRegName[rel_reg]);
         break;
+      case CCRegClass:
+        panic("printReg: CCRegClass but ARM has no CC regs\n");
     }
 }
 
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