From bd0c2d5b0bf512aa5c172fe5676e151913e5e97d Mon Sep 17 00:00:00 2001 From: Mitch Hayenga Date: Thu, 13 Oct 2016 19:22:10 +0100 Subject: isa,arm: Add missing AArch32 FP instructions This commit adds missing non-predicated, scalar floating point instructions. Specifically VRINT* floating point integer rounding instructions and VSEL* floating point conditional selects. Change-Id: I23cbd1389f151389ac8beb28a7d18d5f93d000e7 Reviewed-by: Andreas Sandberg Reviewed-by: Nathanael Premillieu --- src/arch/arm/insts/vfp.cc | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'src/arch/arm/insts/vfp.cc') diff --git a/src/arch/arm/insts/vfp.cc b/src/arch/arm/insts/vfp.cc index 03fdc83fa..c76f97ca6 100644 --- a/src/arch/arm/insts/vfp.cc +++ b/src/arch/arm/insts/vfp.cc @@ -122,6 +122,21 @@ FpRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const return ss.str(); } +std::string +FpRegRegRegCondOp::generateDisassembly(Addr pc, const SymbolTable *symtab) + const +{ + std::stringstream ss; + printMnemonic(ss); + printCondition(ss, cond); + printReg(ss, dest + FP_Reg_Base); + ss << ", "; + printReg(ss, op1 + FP_Reg_Base); + ss << ", "; + printReg(ss, op2 + FP_Reg_Base); + return ss.str(); +} + std::string FpRegRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { -- cgit v1.2.3