From bd0c2d5b0bf512aa5c172fe5676e151913e5e97d Mon Sep 17 00:00:00 2001 From: Mitch Hayenga Date: Thu, 13 Oct 2016 19:22:10 +0100 Subject: isa,arm: Add missing AArch32 FP instructions This commit adds missing non-predicated, scalar floating point instructions. Specifically VRINT* floating point integer rounding instructions and VSEL* floating point conditional selects. Change-Id: I23cbd1389f151389ac8beb28a7d18d5f93d000e7 Reviewed-by: Andreas Sandberg Reviewed-by: Nathanael Premillieu --- src/arch/arm/insts/vfp.hh | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'src/arch/arm/insts/vfp.hh') diff --git a/src/arch/arm/insts/vfp.hh b/src/arch/arm/insts/vfp.hh index f28ab9e1f..de0c62161 100644 --- a/src/arch/arm/insts/vfp.hh +++ b/src/arch/arm/insts/vfp.hh @@ -979,6 +979,27 @@ class FpRegRegRegOp : public FpOp std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; +class FpRegRegRegCondOp : public FpOp +{ + protected: + IntRegIndex dest; + IntRegIndex op1; + IntRegIndex op2; + ConditionCode cond; + + FpRegRegRegCondOp(const char *mnem, ExtMachInst _machInst, + OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, + IntRegIndex _op2, ConditionCode _cond, + VfpMicroMode mode = VfpNotAMicroop) : + FpOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1), op2(_op2), + cond(_cond) + { + setVfpMicroFlags(mode, flags); + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; +}; + class FpRegRegRegRegOp : public FpOp { protected: -- cgit v1.2.3