From 0fa5ed40c471429318c967833592aee0bd361dea Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Tue, 27 Mar 2018 14:23:28 +0100 Subject: arch-arm: Correct mcrr,mrrc disassemble This patch is fixing AArch32 mcrr,mrrc instruction disassemble by printing the correct source/destination registers Change-Id: I3fcffa0349aeee466e7c60ba4d1244824fb65d91 Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/9501 Maintainer: Andreas Sandberg --- src/arch/arm/insts/misc.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/arch/arm/insts') diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc index 9c7a051f5..d4a2ba2d2 100644 --- a/src/arch/arm/insts/misc.cc +++ b/src/arch/arm/insts/misc.cc @@ -153,7 +153,7 @@ MrrcOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const ss << ", "; printIntReg(ss, dest2); ss << ", "; - printIntReg(ss, op1); + printMiscReg(ss, op1); return ss.str(); } @@ -162,7 +162,7 @@ McrrOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); - printIntReg(ss, dest); + printMiscReg(ss, dest); ss << ", "; printIntReg(ss, op1); ss << ", "; -- cgit v1.2.3