From 1f059541d6160931b3bb80bef842c45c2521d642 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 2 Jun 2010 12:58:12 -0500
Subject: ARM: Add a new RegImmOp base class.

---
 src/arch/arm/insts/misc.cc | 10 ++++++++++
 src/arch/arm/insts/misc.hh | 14 ++++++++++++++
 2 files changed, 24 insertions(+)

(limited to 'src/arch/arm/insts')

diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index a5a4e3b32..0eae37de0 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -152,6 +152,16 @@ ImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
     return ss.str();
 }
 
+std::string
+RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+    printMnemonic(ss);
+    printReg(ss, dest);
+    ccprintf(ss, ", #%d", imm);
+    return ss.str();
+}
+
 std::string
 RegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh
index 53281400e..6d78b311a 100644
--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -107,6 +107,20 @@ class ImmOp : public PredOp
     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 };
 
+class RegImmOp : public PredOp
+{
+  protected:
+    IntRegIndex dest;
+    uint64_t imm;
+
+    RegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+             IntRegIndex _dest, uint64_t _imm) :
+        PredOp(mnem, _machInst, __opClass), dest(_dest), imm(_imm)
+    {}
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
 class RegRegOp : public PredOp
 {
   protected:
-- 
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