From 6976b4890a307a2d8584b4e512e3f6d728e59ad5 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 2 Jun 2010 12:58:12 -0500
Subject: ARM: Add a RegRegImmOp base class.

---
 src/arch/arm/insts/misc.cc | 12 ++++++++++++
 src/arch/arm/insts/misc.hh | 17 +++++++++++++++++
 2 files changed, 29 insertions(+)

(limited to 'src/arch/arm/insts')

diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 87d3d1796..a5a4e3b32 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -205,6 +205,18 @@ RegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
     return ss.str();
 }
 
+std::string
+RegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+    printMnemonic(ss);
+    printReg(ss, dest);
+    ss << ", ";
+    printReg(ss, op1);
+    ccprintf(ss, ", #%d", imm);
+    return ss.str();
+}
+
 std::string
 RegRegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh
index 79cec5732..53281400e 100644
--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -189,6 +189,23 @@ class RegRegRegOp : public PredOp
     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 };
 
+class RegRegImmOp : public PredOp
+{
+  protected:
+    IntRegIndex dest;
+    IntRegIndex op1;
+    uint64_t imm;
+
+    RegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+                IntRegIndex _dest, IntRegIndex _op1,
+                uint64_t _imm) :
+        PredOp(mnem, _machInst, __opClass),
+        dest(_dest), op1(_op1), imm(_imm)
+    {}
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
 class RegRegImmImmOp : public PredOp
 {
   protected:
-- 
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