From b8ec21455382c3b5e0e9bc8c0dbcd38b07c567e3 Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Wed, 2 Jun 2010 12:58:16 -0500
Subject: ARM: Implement ARM CPU interrupts

---
 src/arch/arm/insts/static_inst.hh | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

(limited to 'src/arch/arm/insts')

diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh
index 33453bec6..b0eb1a6e9 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -156,7 +156,7 @@ class ArmStaticInst : public StaticInst
 
     static uint32_t
     cpsrWriteByInstr(CPSR cpsr, uint32_t val,
-            uint8_t byteMask, bool affectState)
+            uint8_t byteMask, bool affectState, bool nmfi)
     {
         bool privileged = (cpsr.mode != MODE_USER);
 
@@ -187,7 +187,11 @@ class ArmStaticInst : public StaticInst
                 bitMask = bitMask | (1 << 5);
         }
 
-        return ((uint32_t)cpsr & ~bitMask) | (val & bitMask);
+        bool cpsr_f = cpsr.f;
+        uint32_t new_cpsr = ((uint32_t)cpsr & ~bitMask) | (val & bitMask);
+        if (nmfi && !cpsr_f)
+            new_cpsr &= ~(1 << 6);
+        return new_cpsr;
     }
 
     static uint32_t
-- 
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