From bb6fea91da7c5436d26d6b93f22b2dd5cd6287ba Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 2 Jun 2010 12:58:11 -0500
Subject: ARM: Implement the SRS instruction.

---
 src/arch/arm/insts/mem.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/arch/arm/insts')

diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc
index eb16e42d0..ccac3a25d 100644
--- a/src/arch/arm/insts/mem.cc
+++ b/src/arch/arm/insts/mem.cc
@@ -110,7 +110,7 @@ SrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
         ss << "!";
     }
     ss << ", #";
-    switch (mode) {
+    switch (regMode) {
       case MODE_USER:
         ss << "user";
         break;
-- 
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