From dbee6e0c5406200066b8185fd38fa47dae7cdd2f Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 2 Jun 2010 12:58:11 -0500
Subject: ARM: Add a base class for SRS.

---
 src/arch/arm/insts/mem.cc | 55 +++++++++++++++++++++++++++++++++++++++++++++++
 src/arch/arm/insts/mem.hh | 24 +++++++++++++++++++++
 2 files changed, 79 insertions(+)

(limited to 'src/arch/arm/insts')

diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc
index 394c159d1..eb16e42d0 100644
--- a/src/arch/arm/insts/mem.cc
+++ b/src/arch/arm/insts/mem.cc
@@ -87,6 +87,61 @@ RfeOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
     return ss.str();
 }
 
+string
+SrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    stringstream ss;
+    switch (mode) {
+      case DecrementAfter:
+        printMnemonic(ss, "da");
+        break;
+      case DecrementBefore:
+        printMnemonic(ss, "db");
+        break;
+      case IncrementAfter:
+        printMnemonic(ss, "ia");
+        break;
+      case IncrementBefore:
+        printMnemonic(ss, "ib");
+        break;
+    }
+    printReg(ss, INTREG_SP);
+    if (wb) {
+        ss << "!";
+    }
+    ss << ", #";
+    switch (mode) {
+      case MODE_USER:
+        ss << "user";
+        break;
+      case MODE_FIQ:
+        ss << "fiq";
+        break;
+      case MODE_IRQ:
+        ss << "irq";
+        break;
+      case MODE_SVC:
+        ss << "supervisor";
+        break;
+      case MODE_MON:
+        ss << "monitor";
+        break;
+      case MODE_ABORT:
+        ss << "abort";
+        break;
+      case MODE_UNDEFINED:
+        ss << "undefined";
+        break;
+      case MODE_SYSTEM:
+        ss << "system";
+        break;
+      default:
+        ss << "unrecognized";
+        break;
+    }
+    return ss.str();
+}
+
 void
 Memory::printInst(std::ostream &os, AddrMode addrMode) const
 {
diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh
index ae3437120..50f718b99 100644
--- a/src/arch/arm/insts/mem.hh
+++ b/src/arch/arm/insts/mem.hh
@@ -87,6 +87,30 @@ class RfeOp : public PredOp
     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 };
 
+// The address is a base register plus an immediate.
+class SrsOp : public PredOp
+{
+  public:
+    enum AddrMode {
+        DecrementAfter,
+        DecrementBefore,
+        IncrementAfter,
+        IncrementBefore
+    };
+  protected:
+    uint32_t regMode;
+    AddrMode mode;
+    bool wb;
+
+    SrsOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+          uint32_t _regMode, AddrMode _mode, bool _wb)
+        : PredOp(mnem, _machInst, __opClass),
+          regMode(_regMode), mode(_mode), wb(_wb)
+    {}
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
 class Memory : public PredOp
 {
   public:
-- 
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